A question about Xapp524 written by Marc Defossez

Question

Hi Marc Defossez,
I have a question about Xapp524. Pls check the figure below. I find the frame pattern should be "00001111". But in the source code AdcFrame.vhd, I find the frame pattern is IntPatternA, IntPatternB, IntPatternC or IntPatternD which donot include "00001111". I cannot understand why. Could you explain it to more detail?
Thanks
 Rgds
Orange

Answer 1

Hi, Thanks for your reply. I don't know what version  it  is. But in the xapp524 “readme.txt” is found
1. REVISION HISTORY
Readme
Date                      Version                            Revision Description
=========================================================================
19/08/2012              1.0                                Initial Xilinx release.
=========================================================================
So i guess the version may be 1.0.
The code makes me confused is in the AdcFrame.vhd.   
-- A std_logic_vector is converted to a string.
function stdlvec_to_str(inp: std_logic_vector) return string is
variable temp: string(inp'left+1 downto 1) := (others => 'X');
begin
    for i in inp'reverse_range loop
        if (inp(i) = '1') then
            temp(i+1) := '1';
        elsif (inp(i) = '0') then
            temp(i+1) := '0';
        end if;
   end loop;
return temp;
end function stdlvec_to_str;
-- A string is converted to a std_logic_vector.
function str_to_stdlvec(Inp: string) return std_logic_vector is
variable Temp : std_logic_vector(Inp'range) := (others => 'X');
begin
    for i in Inp'range loop
        if (Inp(i) = '1') then
           Temp(i) := '1';
        elsif (Inp(i) = '0') then
            Temp(i) := '0';
        end if;
   end loop;
return Temp;
end function str_to_stdlvec;
-- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
-- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
-- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
function FrmBits (Bits : integer) return integer is
variable Temp : integer;
begin
if (Bits = 12) then
Temp := 12;
elsif (Bits = 14) then
Temp := 16;
elsif (Bits = 16) then
Temp := 16;
end if;
return Temp;
end function FrmBits;
-- Word symmetry check
-- A word (16-bit) is checked for bit pair symmetry
-- Example: In one byte there are 16 possible symmetry positions.
-- 00000000, 00000011, 00001100, 00001111,
-- 00110000, 00110011, 00111100, 00111111,
-- 11000000, 11000011, 11001100, 11001111,
-- 11110000, 11110011, 11111100, 11111111,
-- Bit_7=Bit_6, Bit_5=Bit_4, Bit_3=Bit_2, and Bit_1=Bit_0
function SymChck (Inp: std_logic_vector) return std_logic is
variable Temp : std_logic_vector ((Inp'left-1)/2 downto 0) := (others => '0');
variable Sym : std_logic := '0';
begin
for n in (Inp'left-1)/2 downto 0 loop
Temp(n) := Inp((n*2)+1) xor Inp(n*2);
Sym := Temp(n) or Sym;
end loop;
assert false
report CR & " Pattern XORed/ORed = " & stdlvec_to_str(Temp) & CR
severity note;
return Sym;
end function SymChck;
-- When a symmetric byte, bit pattern is found, make the requested pattern rotate
-- by one bit to become a non-symmetric pattern.
function BitShft(Inp: std_logic_vector; Wire: integer) return std_logic_vector is
variable Temp : std_logic_vector (Inp'range):= (others => '0');
begin
-- Bit shift all bits.
-- Example: 16-bit frame word = 11111111_00000000 or 00000000_11110000
-- After shifting the word returned looks as: 11111110_00000001 and 00000000_01111000
if (SymChck(Inp) = '0') then
if (Wire = 1 ) then -- 1-wire, shift 15-bits
for n in Inp'left downto 0 loop
if (n /= 0) then
Temp(n) := Inp(n-1);
elsif (n = 0) then
Temp(Temp'right) := Inp(Inp'left);
end if;
end loop;
else -- (Wire = 2) -- 2-wire, shift 8-bits
for n in (Inp'left-8) downto 0 loop
if (n /= 0) then
Temp(n) := Inp(n-1);
elsif (n = 0) then
Temp(Temp'right) := Inp(Inp'left-8);
end if;
end loop;
end if;
elsif (SymChck(Inp) = '1') then
-- Don't do anything, return the word as it came in.
Temp := Inp;
end if;
assert false
report CR &
" Pattern Shifted = " & stdlvec_to_str(Temp) & CR &
" Comparator Value A = " & stdlvec_to_str(Temp(15 downto 8)) & CR &
" Comparator Value B = " & stdlvec_to_str(Temp(7 downto 0)) & CR
severity note;
return Temp;
end function BitShft;
-- Bit swap operation:
-- Bit n of the output string gets bit n-1 of the input. ex: out(7) <= In(6).
-- Bit n-1 of the output string gets bit n of the input. ex: out(6) <= In(7).
-- Bit n-2 of the output string gets bit n-3 of the input. ex: out(5) <= In(4).
-- Bit n-3 of the output string gets bit n-2 of the input. ex: out(4) <= In(5).
-- and etcetera....
-- This: Bit_7, Bit_6, Bit_5, Bit_4, Bit_3, Bit_2, Bit_1, Bit_0.
-- Results in: Bit_6, Bit_7, Bit-$, Bit_5, Bit_2, Bit_3, Bit_0, Bit_1.
function BitSwap(Inp: std_logic_vector) return std_logic_vector is
variable Temp : std_logic_vector (Inp'range);
begin
for n in (Inp'left-1)/2 downto 0 loop
Temp((n*2)+1) := Inp(n*2);
Temp(n*2) := Inp((n*2)+1);
end loop;
assert false
report CR &
" Pattern Bit Swapped = " & stdlvec_to_str(Temp) & CR &
" Comparator Value C = " & stdlvec_to_str(Temp(15 downto 8)) & CR &
" Comparator Value D = " & stdlvec_to_str(Temp(7 downto 0)) & CR
severity note;
return Temp;
end function BitSwap;
function TermOrNot (Term : integer) return boolean is
begin
if (Term = 0) then
return FALSE;
else
return TRUE;
end if;
end TermOrNot;
-- Constants
-- Transform the pattern STRING into a std_logic_vector.
constant IntPattern :
std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := str_to_stdlvec(C_FrmPattern);
-- Shift the pattern for one bit.
constant IntPatternBitShifted :
std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitShft(IntPattern, C_AdcWireInt);
-- Bit swap the by one bit shifted pattern.
constant IntPatternBitSwapped :
std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitSwap(IntPatternBitShifted);
-- Define the bytes for pattern comparison.
constant IntPatternA : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
    IntPatternBitShifted(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);
constant IntPatternB : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
    IntPatternBitShifted((FrmBits(C_AdcBits)/2)-1 downto 0);
constant IntPatternC : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
    IntPatternBitSwapped(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);
constant IntPatternD : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
    IntPatternBitSwapped((FrmBits(C_AdcBits)/2)-1 downto 0);
The intPatternA, intPatternB, intPatternC and intPatternD are used as a trainning pattern for the frameclock. As I think, the training pattern should be C_FrmPattern(C_FrmPattern is "11110000"  when  adcbits  is 16 and the wire is 2). Why do you use intPatternA to intPatternD as the training pattern? 
 The AdcFrame.vhd is attached.