ADC DDR source synchronous timing constraints help

Question

Hi all,
  I am using a virtex 5 xc5fx200T-1ff1738 with ISE 12.4 to capture data from an ADC (KAD5512p-50 http://www.intersil.com/content/dam/Intersil/documents/kad5/kad5512p-50.pdf).
I calculate my timing constraints as follows:
TIMEGRP "ADC_1_DP_TIM_GRP" OFFSET = IN 1.713ns VALID 1.487ns BEFORE ADC_1_CLK_P_IN RISING;
TIMEGRP "ADC_1_DP_TIM_GRP" OFFSET = IN 1.823ns VALID 1.629ns BEFORE ADC_1_CLK_P_IN FALLING;
ADC clock period (DDR) = 2ns
ADC clk->q rising max = 0.120ns
ADC clk->q rising min = -0.260ns
ADC clk->q falling max = 0.230ns
ADC clk->q falling min = -0.160ns
The board latency of the ADC clock to the FPGA is 0.424ns.
Each ADC data pin is trace matched between N and P, but sadly not between each bit.
Bit     Delay           Clk->Data delay (0.424ns - data delay)
0        0.481ns       0.057ns
1        0.480ns       0.056ns
2        0.481ns       0.057ns
3        0.479ns       0.055ns
4        0.481ns       0.057ns
5        0.390ns      -0.034ns
6        0.480ns       0.056ns
7        0.479ns       0.055ns
8        0.430ns       0.006ns
9        0.473ns       0.049ns
10      0.481ns       0.057ns
11      0.480ns        0.056ns
Delta of the minimum and maximum clk->data board latency = ( 0.057ns - -0.034ns ) = 0.023ns    (Right?)
From this I calculate:
Rising edge offset by:
  ADC clock period - clk->q falling max - max board clk->q delay
    = 2ns - 0.230ns - 0.057ns = 1.713ns
Rising edge valid time:
  ADC clock period - clk->q falling max - clk->q rising min - ( Delta of the minimum and maximum clk->data board latency )
    = 2ns - 0.230ns - 0.260ns - 0.023ns = 1.487ns
Falling edge offset by:
  ADC clock period - clk->q rising max - max board clk->q delay
    = 2ns - 0.120ns - 0.057ns = 1.823ns
Falling edge valid time:
  ADC clock period - clk->q rising max - clk->q falling min - ( Delta of the minimum and maximum clk->data board latency )
    = 2ns - 0.120ns - 0.160ns - 0.023ns = 1.629ns
The FPGA needs a window of 1.77ns( 1.55ns setup time + 0.16ns hold time according to the data sheet DS202 v.5.4 table 93, Tpsdcm0/Tphdcm0), which I obviously do not have given these constraints.  Am I calculating this wrong?
I want to use the phase shift of the DCM to move to the clock to the "data eye."  Are my constraints caluclated properly?
 

Answer 1

I haven't analyzed your numbers carefully, but at first glance, this looks more or less correct. There appears to be a simple math error in calculating your data skew : (0.057ns - -0.034ns ) = 0.023ns ; it looks like you added the negative number instead of subtracting it (which makes things worse).
Thus your overall window is small - probably around 1.419ns (correcting for your error above). This is too small to capture with global clock capture using the DCM (yes, you are interpreting Tpsdcm_0/Tphdcm_0 correctly)
The only option for static capture is to use ChipSync; bring the clock in on a CCIO and use a BUFIO to capture the data. Done this way your timing is Tpscs/Tphcs, which requires a data window of only 1.370ns (leaving a whopping 49ps of margin). Of course, this is best case - if you have duty cycle errors or other board/signal integrity issues, it will come out of this margin.
There are a few things that make this better. The Tpscs/Tphcs is measured with LVCMOS25 - using LVDS will probably make it better, but we can't really quantify how much.
Also, the board delay is mostly PVT independent - you could compensate for the static error using the IDELAY. In particular you could add one tap of delay to to data bit 5, which will add approximately 78ps to that one bit - bringing it more in line with the rest. Your overall skew would the be 57-6 = 49ps, instead of 57--34 = 91ps.
To center the data eye, you would put IDELAYs on both the clock and the data. Keep the data delays as small as possible (ideally 0 on all bits except bit 5 which is 1), and then delay the IDELAY on the clock to make the data window work. You may need to adjust your OFFSET IN constraints to match the fact that you are pushing the clock forward (subtract 2ns from the OFFSET IN to indicate that the data window comes after the clock edge, not before) - thus your commands will be of the format
TIMEGRP "ADC_1_DP_TIM_GRP" OFFSET = IN <x> ns VALID <y>ns BEFORE ADC_1_CLK_P_IN RISING;
Where <x> will be a small negative number - on the order of 1.172-2.000.
However, this will all only work if the clock is on a CC pair, not a GC pair (on Virtex-5 these were different), and that all LVDS pairs are in the same I/O bank as the clock pair. If your board is already designed, then you probably can't change this.
If you can't use chip-sync (and even at that, timing is really tight), then you will have to use some sort of dynamic calibration.
Avrum