Fail to Meet Timing Constraint with Xilinx 9.2i Suite
Hi,
I've been trying to p&r the OpenSPARC T1 v1.6 with either 1core/1thread or 1core/4threads using the Xilinx 9.2i EDK with the latest updates to no avail. It looks like the design just refuses to meet a timing constraint. I have no problem doing the p&r using Xilinx ISE/EDK 10.1(and getting a working bitfile), but since the original EDK project was designed using v9.2(from looking at the system.xmp file) I was wondering if anyone was able to successfully create a bitfile for the OpenSPARC T1 using v9.2 of the Xilinx tools. I tried using a fresh tarball (with the supplied sparc.edf file) and following the instructions in OpenSPARCT1_DVGuide.pdf using the 9.2i suite, but again, I had the same results (design failed to meet timing). Any help on the issue is greatly appreciated. For reference, here is the constraint not met.
*TS_clock_generator_0_clock_generator_0_clkgen_core_inst_clkgen_arch_inst_using_dcm_arch_model_dcm_array_1__using_dcm_module_inst_dcm_module_inst_CLK0_BUF =
PERIOD TIMEGRP "clock_generator_0_clock_generator_0_clkgen_core_inst_clkgen_arch_inst_using_dcm_arch_model_dcm_array_1__using_dcm_module_inst_dcm_module_inst_CLK0_BUF"
TS_clock_generator_0_clock_generator_0_clkgen_core_inst_clkgen_arch_inst_using_dcm_arch_model_dcm_array_0__using_dcm_module_inst_dcm_module_inst_CLKFX_BUF HIGH 50% From looking at the Xilinx Timing Analyzer, it looked like paths from the microblaze processor the the lmbrams was the issue.
Oleg
We have gotten those errors from time to time as well. One thing we did to get around this was to set the following option in the system.xmp file:
EnableParTimingError: 1
If you are having success with ISE/EDK 10.1, that's great. I would stick with it. We will be updating the OpenSPARC T1 project for EDK 10.1 pretty soon anyway.
formalGuy
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Design does not meet the timing constraints of the specified clock
Hi,
I am using labVIEW FPGA 2011 and FlexRIO 7965R (virtex 5 SX95T). I am trying to use multiple simple dual port RAMs (generated through xilinx coregen tool) in cascade. The data read from one memory block is written to the next memory block and so on. I want the design to run as fast as possible. I have used SCTL rate of 346MHz in my design. But when i compile the code, timing violation error occurs. And the maximum clock rate achieved is 291.25MHz. The timing vilation analysis window always show the feedback node and controller as paths which failed to meet the timing contraints. I have also used DMA and VI Scoped FIFOs in my design for data input and output.
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Attachments:
Projec_Memory Block.zip 309 KB
Block Memory Generator_GUI.zip 236 KBHave you taken a look around the forums?
http://forums.ni.com/t5/LabVIEW/Compile-Error-in-FlexRIO-FPGA-when-using-derived-clock/td-p/1617226
What is the exact timing violation error you receive? Depending on how your feedback nodes are used it can slow down the clock rate from the desired clock rate. This is what I normally use as a reference for making my code operate more quickly:
http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/registers/#Register_Timing
http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpga/fpga_timed_loop/
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Problems with IO timing constraints
I am developing a system for Virtex-6 FPGA under ISE environment.
Now I have several I/O pins that need to be constrained in timing.
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Hello All,
I have a SubVI that uses block memory, which has been created using Xilinx "Block Memory Generator 8.1". I have configured this block memory to be a "Single Port ROM", and I use a coefficient file to initialize the memory contents. In simulation mode, everything works as it should.
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http://www.cs.nyu.edu/~aditya/Compilation_Log_100.txt
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HDL Interface Node (UsingFilterCore.vi) and "timing constraint" error when compiling
I'm trying to use the HDL interface node in LV8 FPGA with a PCI-5640R and had the "timing constraint" error when compiling my VI, however, the same VI was successfully compiled on a CRIO-9104, it seems the FPGA on PCI-5640R is not good as the one on CRIO-9104, or I'm not using it right. could you please kindly help me out?
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Can you help me out？ Thanks very much !
Message Edited by Jerry_L on 03-26-2006 09:28 PM
Message Edited by Jerry_L on 03-26-2006 09:29 PMHi Jerry,
I'm just tried to make all these steps by myself (http://zone.ni.com/devzone/cda/tut/p/id/3516). I have generated FIR filter using Xilinx ISE and got *.VHD file which was going to use in HDL Node.
In the Parameters tab of the HDL Interface Node configuration dialog, double-click in the Names column to add parameters. Create parameters as shown below.
Next, switch to the Code tab. Notice that your parameters now appear in the entity section. To complete the next two sections of code, you will need to refer to the filt.vhd file that you generated earlier and interface the filter core to the LabVIEW FPGA execution system.
1. The first problem I met was integrating VHDL code from earlier generated *.VHD file to CODE tab in properties of HDL Node. Content of entity section in *.VHD is not the same that in your attached file. Please check it in attached files. I'm sure this is the main reasen of problem.
Next, switch to the External Files tab. Click the Add File button and select the filt.edn file that you created earlier. This is the EDIF netlist file that you generated earlier.
2. I have no idea where can I get it and when during filter generation using Xilinx ISE it was generated too. How can I get it? I had to use your attached file filt.edn.
3. After that I have made the same schematics like you have in your VI FPGA and try to run. But I've got two error messages:
HDL Interfave node: enable chain not handled. Details: Refer to the documentation for the correct assignments for the enable_out output from your HDL code.
HDL Interfave node: output not handled. Details: Right-click the node, select Configure to open the Configure HDL Interface Node dialog box, and use the Code tab to handle all output parameters.
Actually I need to model FIR filter:
Bandwidth 200-600 Hz
Sampling 8 KHz
Attenuation 80 dB
That's why I tried to follow all these steps by myself to understand how does it work.
Thanks a lot.
Nikita
Attachments:
Filter1.vi 16 KB -
The compilation of my labview fpga vi fails with the error message "LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD".
In the 'final timing (place and route)' report, the requested frequencies are all below the maximum frequencies and the compilation error message is only displayed at the very end on the 'summary' page.
I tried to optimize my labview fpga vi with pipelining, but had no success.
Can anybody offer some advice on how to debug fpga code with this error? Is this really a timing error or something else?
Software:
Labview 2011, fpga 2011, xilinx tools 12.4 sp1
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
The Xilinx log of the compilation run is attached.
Also, this issue was already discussed in this thread ~6 months ago, but no satisfying answer was offered so far...
Thanks,
Fabrizio
Attachments:
xilinxlogc.txt 2313 KBHi Kyle,
the problem is: I have one computer which compiles the VI successfully and a second one which shows that error. Both use the same software setup (LV2011SP1+RT+FPGA from DS2012-01). Both use the same project file - atleast SVN shows no difference.
- You can have one FPGA VI where one computer is compiling successful and a second one complains. (Btw. I have a SRQ running in Germany on this topic.)
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All those problems didn't occur on my RT-FPGA projects in LV2010SP1. I'm not pleased...
Best regards,
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Compilation failed due to timing violations, Getting Xflow error and resources over use.
Hi,
I am extensively using Fixed point math library functions which i have downloaded from NI website in my FPGA application.I am getting following errors while compiling the code.
I would like to know is there any limitations in using fixed point functions?
I am configuring all funtions as a 64 bit word length and 32 bit integer length in cofig parameter set up and all are outside the timed loop.
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Status: Compilation failed due to timing violations.
The compile process reported a timing violation.
Suggestions for eliminating the problem:
* For Timed Loops with timing violations
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- Reduce the number of nested case structures
* Reduce clock rates if possible
* Recompile
Refer to the LabVIEW Help for more information about resolving compilation errors. Click the Help button to display the LabVIEW Help.
Compilation Summary
Device Utilization Summary:
Number of BUFGMUXs 2 out of 16 12%
Number of External IOBs 214 out of 484 44%
Number of LOCed IOBs 214 out of 214 100%
Number of MULT18X18s 69 out of 96 71%
Number of SLICEs 4387 out of 14336 30%
Clock Rates: (Requested rates are adjusted for jitter and accuracy)
Base clock: 40 MHz Onboard Clock
Requested Rate: 40.408938MHz
Achieved Rate: 36.974044MHz <<<=== Timing Violationlion-o wrote:
The Fixed Point Library is certainly not a demo, and we encourage you to use it extensively.
Really? "Demo" is perhaps too strong a word, but the NI Labs page says that the toolkits there "aren't quite ready for release" and are "experimental prototype"s. My understanding was that they work, but are only meant to show potential future products and get feedback on them. If this is not the case, perhaps the wording needs to be changed.
I know I wouldn't want to be using something throughout my code and then find out that it is not supported when the next LV version came out because it was only a prototype. Can you promise support into the future for these? If you can't, that should be clearly stated.
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Hi all,
I am using a virtex 5 xc5fx200T-1ff1738 with ISE 12.4 to capture data from an ADC (KAD5512p-50 http://www.intersil.com/content/dam/Intersil/documents/kad5/kad5512p-50.pdf).
I calculate my timing constraints as follows:
TIMEGRP "ADC_1_DP_TIM_GRP" OFFSET = IN 1.713ns VALID 1.487ns BEFORE ADC_1_CLK_P_IN RISING;
TIMEGRP "ADC_1_DP_TIM_GRP" OFFSET = IN 1.823ns VALID 1.629ns BEFORE ADC_1_CLK_P_IN FALLING;
ADC clock period (DDR) = 2ns
ADC clk->q rising max = 0.120ns
ADC clk->q rising min = -0.260ns
ADC clk->q falling max = 0.230ns
ADC clk->q falling min = -0.160ns
The board latency of the ADC clock to the FPGA is 0.424ns.
Each ADC data pin is trace matched between N and P, but sadly not between each bit.
Bit Delay Clk->Data delay (0.424ns - data delay)
0 0.481ns 0.057ns
1 0.480ns 0.056ns
2 0.481ns 0.057ns
3 0.479ns 0.055ns
4 0.481ns 0.057ns
5 0.390ns -0.034ns
6 0.480ns 0.056ns
7 0.479ns 0.055ns
8 0.430ns 0.006ns
9 0.473ns 0.049ns
10 0.481ns 0.057ns
11 0.480ns 0.056ns
Delta of the minimum and maximum clk->data board latency = ( 0.057ns - -0.034ns ) = 0.023ns (Right?)
From this I calculate:
Rising edge offset by:
ADC clock period - clk->q falling max - max board clk->q delay
= 2ns - 0.230ns - 0.057ns = 1.713ns
Rising edge valid time:
ADC clock period - clk->q falling max - clk->q rising min - ( Delta of the minimum and maximum clk->data board latency )
= 2ns - 0.230ns - 0.260ns - 0.023ns = 1.487ns
Falling edge offset by:
ADC clock period - clk->q rising max - max board clk->q delay
= 2ns - 0.120ns - 0.057ns = 1.823ns
Falling edge valid time:
ADC clock period - clk->q rising max - clk->q falling min - ( Delta of the minimum and maximum clk->data board latency )
= 2ns - 0.120ns - 0.160ns - 0.023ns = 1.629ns
The FPGA needs a window of 1.77ns( 1.55ns setup time + 0.16ns hold time according to the data sheet DS202 v.5.4 table 93, Tpsdcm0/Tphdcm0), which I obviously do not have given these constraints. Am I calculating this wrong?
I want to use the phase shift of the DCM to move to the clock to the "data eye." Are my constraints caluclated properly?
I haven't analyzed your numbers carefully, but at first glance, this looks more or less correct. There appears to be a simple math error in calculating your data skew : (0.057ns - -0.034ns ) = 0.023ns ; it looks like you added the negative number instead of subtracting it (which makes things worse).
Thus your overall window is small - probably around 1.419ns (correcting for your error above). This is too small to capture with global clock capture using the DCM (yes, you are interpreting Tpsdcm_0/Tphdcm_0 correctly)
The only option for static capture is to use ChipSync; bring the clock in on a CCIO and use a BUFIO to capture the data. Done this way your timing is Tpscs/Tphcs, which requires a data window of only 1.370ns (leaving a whopping 49ps of margin). Of course, this is best case - if you have duty cycle errors or other board/signal integrity issues, it will come out of this margin.
There are a few things that make this better. The Tpscs/Tphcs is measured with LVCMOS25 - using LVDS will probably make it better, but we can't really quantify how much.
Also, the board delay is mostly PVT independent - you could compensate for the static error using the IDELAY. In particular you could add one tap of delay to to data bit 5, which will add approximately 78ps to that one bit - bringing it more in line with the rest. Your overall skew would the be 57-6 = 49ps, instead of 57--34 = 91ps.
To center the data eye, you would put IDELAYs on both the clock and the data. Keep the data delays as small as possible (ideally 0 on all bits except bit 5 which is 1), and then delay the IDELAY on the clock to make the data window work. You may need to adjust your OFFSET IN constraints to match the fact that you are pushing the clock forward (subtract 2ns from the OFFSET IN to indicate that the data window comes after the clock edge, not before) - thus your commands will be of the format
TIMEGRP "ADC_1_DP_TIM_GRP" OFFSET = IN <x> ns VALID <y>ns BEFORE ADC_1_CLK_P_IN RISING;
Where <x> will be a small negative number - on the order of 1.172-2.000.
However, this will all only work if the clock is on a CC pair, not a GC pair (on Virtex-5 these were different), and that all LVDS pairs are in the same I/O bank as the clock pair. If your board is already designed, then you probably can't change this.
If you can't use chip-sync (and even at that, timing is really tight), then you will have to use some sort of dynamic calibration.
Avrum
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The core clock is slow or no core clock connected for this ILA or the ILA core may not meet timing.
[Labtools 27-1395] Unable to arm ILA 'hw_ila_1'. The core clock is slow or no core clock connected for this ILA or the ILA core may not meet timing.
I have seen related forums but cant get any help. My timing is completely fine. I tried all JTAG frequencies from 1.5MHZ to `12 MHZ. My clk for ILA core runs at 100 MHZ.
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Check the message at the bottom of the ChipScope Analyzer window. If it is similar to "Waiting for trigger, Sample buffer has 0 samples(0%)," proceed as follows:
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BUFG is not used on ICON's JTAG clock
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Thank you for using Apple Support Communities
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You can make the iCloud calendar your default calendar for all new events. In Calendar on OS X Mountain Lion, choose Calendar > Preferences > General, or in OS X Lion, choose iCal > Preferences > Generaland under the Default Calendar heading, select one of the Calendars under the iCloud heading. Close the Preferences window to save this change.
If recent changes simply don't appear, try forcing Calendar or iCal to refresh by selecting Refresh All from theCalendar menu.
Make sure your account was successfully created in Calendar on your Mac (or iCal). After upgrading to iCloud Calendar, you may need to quit and reopen Calendar (or iCal). To confirm your account is configured correctly in iCal:
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Open Calendar (or iCal) Preferences.
Click Accounts. You should see an account with your iCloud member name entered.
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Quit Calendar (or iCal).
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Close System Preferences and wait about a minute.
Open System Preferences and choose iCloud.
Replace the checkmark next to Calendars.
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Restart your computer. This may sound simple, but it does reinitialize your network and application settings and can frequently resolve issues.
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Dear Team,
Can you please help me by providing the BAPI name for creating the outbound delivery for Scheduling Agreement in SAP SD .
I faile to create outbound delivery with reference to scheduling agreement by using BAPI_OUTB_DELIVERY_CREATE_SLS.
The system says "missing data in the BAPI interface: VBAK VBTYP E". It seems another FM should be used for scheduling agreement only.
Thank you for your help in this regard .Hi Raghu.
As much as I don't want to do this but just to resolve this error I created an enhancement implementation in include LV50R_CREACSV form routine dcs_check_so_vs_interface and modified VBTYP to blank to avoid that error message.
Got the tip from this thread http://scn.sap.com/thread/1972059
Unless... anybody has a brighter idea (without modifying the standards)?
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