HDL Interface Node (UsingFilterCore.vi) and "timing constraint" error when compiling

Question

I'm trying to use the HDL interface node in LV8 FPGA with a PCI-5640R and had the "timing constraint" error when compiling my VI, however, the same VI was successfully compiled on a CRIO-9104, it seems the FPGA on PCI-5640R is not good as the one on CRIO-9104, or I'm not using it right. could you please kindly help me out?
I tested it with the sample code downloaded from NI website
( http://zone.ni.com/devzone/conceptd.nsf/webmain/456722DDDE17986A86256E7B0065EE6F ) which demonstrates using an IP core for a filter. To simplify it, I only keep the HDL Interface Node and the While Loop (see "UsingFilterCore.vi" in attached zip file), and then I created 2 projects including this VI (1 for CRIO-9104, in sub folder "CRIO-9104", the other for PCI-5640R, in sub folder "IFRIO 5640"). When opening the 2 projects separately in LV8.0 and selecting the VI for compile, the one for 9104 passed and the other failed. Here I attach the source code, error message screenshot and the NIReport from MAX, hope you can reduplicate the problem.
Can you help me out？ Thanks very much !
Message Edited by Jerry_L on 03-26-2006 09:28 PM
Message Edited by Jerry_L on 03-26-2006 09:29 PM

Answer 1

Hi Jerry,
I'm just tried to make all these steps by myself (http://zone.ni.com/devzone/cda/tut/p/id/3516). I have generated FIR filter using Xilinx ISE and got *.VHD file which was going to use in HDL Node.
In the Parameters tab of the HDL Interface Node configuration dialog, double-click in the Names column to add parameters. Create parameters as shown below.
Next, switch to the Code tab. Notice that your parameters now appear in the entity section. To complete the next two sections of code, you will need to refer to the filt.vhd file that you generated earlier and interface the filter core to the LabVIEW FPGA execution system.
1. The first problem I met was integrating VHDL code from earlier generated *.VHD file to CODE tab in properties of HDL Node. Content of entity section in *.VHD is not the same that in your attached file. Please check it in attached files. I'm sure this is the main reasen of problem.
Next, switch to the External Files tab. Click the Add File button and select the filt.edn file that you created earlier. This is the EDIF netlist file that you generated earlier.
2. I have no idea where can I get it and when during filter generation using Xilinx ISE it was generated too. How can I get it? I had to use your attached file filt.edn.
3. After that I have made the same schematics like you have in your VI FPGA and try to run. But I've got two error messages:
HDL Interfave node: enable chain not handled. Details: Refer to the documentation for the correct assignments for the enable_out output from your HDL code.
HDL Interfave node: output not handled. Details: Right-click the node, select Configure to open the Configure HDL Interface Node dialog box, and use the Code tab to handle all output parameters. 
Actually I need to model FIR filter:
Bandwidth 200-600 Hz
Sampling 8 KHz
Attenuation 80 dB
That's why I tried to follow all these steps by myself to understand how does it work.
Thanks a lot.
Nikita
Attachments:
Filter1.vi ‏16 KB