BINARY in statement exception

Hello,guys:
I am a green hand in EJB.and Now I'm using elipse+lomboz developing the project ,and the server is JBoss.today I got an Exception in delpoying a cmp.the information is below:
org.jboss.deployment.DeploymentException: Error while creating table MLMEMBER; - nested throwable: (java.sql.SQLException: Unexpected token: BINARY in statement [CREATE TABLE MLMEMBER (email VARCHAR(250) BINARY NOT NULL, name VARCHAR(250) BINARY, CONSTRAINT PK_MLMEMBER PRIMARY KEY (email))])
     at org.jboss.ejb.plugins.cmp.jdbc.JDBCStartCommand.createTable(JDBCStartCommand.java:175)
     at org.jboss.ejb.plugins.cmp.jdbc.JDBCStartCommand.execute(JDBCStartCommand.java:84)
     at org.jboss.ejb.plugins.cmp.jdbc.JDBCStoreManager.startStoreManager(JDBCStoreManager.java:457)
     at org.jboss.ejb.plugins.cmp.jdbc.JDBCStoreManager.start(JDBCStoreManager.java:369)
     at org.jboss.ejb.plugins.CMPPersistenceManager.start(CMPPersistenceManager.java:198)
     at org.jboss.ejb.EntityContainer.start(EntityContainer.java:376)
     at org.jboss.ejb.Container.invoke(Container.java:782)
     at org.jboss.ejb.EntityContainer.invoke(EntityContainer.java:1058)
     at org.jboss.mx.server.MBeanServerImpl.invoke(MBeanServerImpl.java:517)
     at org.jboss.system.ServiceController$ServiceProxy.invoke(ServiceController.java:1003)
     at $Proxy4.start(Unknown Source)
     at org.jboss.system.ServiceController.start(ServiceController.java:413)
     at sun.reflect.GeneratedMethodAccessor4.invoke(Unknown Source)
     at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
     at java.lang.reflect.Method.invoke(Unknown Source)
     at org.jboss.mx.capability.ReflectedMBeanDispatcher.invoke(ReflectedMBeanDispatcher.java:284)
     at org.jboss.mx.server.MBeanServerImpl.invoke(MBeanServerImpl.java:517)
     at org.jboss.util.jmx.MBeanProxy.invoke(MBeanProxy.java:174)
     at $Proxy21.start(Unknown Source)
     at org.jboss.ejb.EjbModule.startService(EjbModule.java:404)
     at org.jboss.system.ServiceMBeanSupport.start(ServiceMBeanSupport.java:165)
     at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
     at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
     at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
     at java.lang.reflect.Method.invoke(Unknown Source)
     at org.jboss.mx.capability.ReflectedMBeanDispatcher.invoke(ReflectedMBeanDispatcher.java:284)
     at org.jboss.mx.server.MBeanServerImpl.invoke(MBeanServerImpl.java:517)
     at org.jboss.system.ServiceController$ServiceProxy.invoke(ServiceController.java:1003)
     at $Proxy4.start(Unknown Source)
     at org.jboss.system.ServiceController.start(ServiceController.java:413)
     at sun.reflect.GeneratedMethodAccessor4.invoke(Unknown Source)
     at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
     at java.lang.reflect.Method.invoke(Unknown Source)
     at org.jboss.mx.capability.ReflectedMBeanDispatcher.invoke(ReflectedMBeanDispatcher.java:284)
     at org.jboss.mx.server.MBeanServerImpl.invoke(MBeanServerImpl.java:517)
     at org.jboss.util.jmx.MBeanProxy.invoke(MBeanProxy.java:174)
     at $Proxy15.start(Unknown Source)
     at org.jboss.ejb.EJBDeployer.start(EJBDeployer.java:395)
     at org.jboss.deployment.MainDeployer.start(MainDeployer.java:814)
     at org.jboss.deployment.MainDeployer.deploy(MainDeployer.java:627)
     at org.jboss.deployment.MainDeployer.deploy(MainDeployer.java:591)
     at sun.reflect.GeneratedMethodAccessor12.invoke(Unknown Source)
     at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
     at java.lang.reflect.Method.invoke(Unknown Source)
     at org.jboss.mx.capability.ReflectedMBeanDispatcher.invoke(ReflectedMBeanDispatcher.java:284)
     at org.jboss.mx.server.MBeanServerImpl.invoke(MBeanServerImpl.java:517)
     at org.jboss.util.jmx.MBeanProxy.invoke(MBeanProxy.java:174)
     at $Proxy3.deploy(Unknown Source)
     at org.jboss.deployment.scanner.URLDeploymentScanner.deploy(URLDeploymentScanner.java:435)
     at org.jboss.deployment.scanner.URLDeploymentScanner.scanDirectory(URLDeploymentScanner.java:656)
     at org.jboss.deployment.scanner.URLDeploymentScanner.scan(URLDeploymentScanner.java:507)
     at org.jboss.deployment.scanner.AbstractDeploymentScanner.startService(AbstractDeploymentScanner.java:266)
     at org.jboss.system.ServiceMBeanSupport.start(ServiceMBeanSupport.java:165)
     at sun.reflect.GeneratedMethodAccessor5.invoke(Unknown Source)
     at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
     at java.lang.reflect.Method.invoke(Unknown Source)
     at org.jboss.mx.capability.ReflectedMBeanDispatcher.invoke(ReflectedMBeanDispatcher.java:284)
     at org.jboss.mx.server.MBeanServerImpl.invoke(MBeanServerImpl.java:517)
     at org.jboss.system.ServiceController$ServiceProxy.invoke(ServiceController.java:1003)
     at $Proxy0.start(Unknown Source)
     at org.jboss.system.ServiceController.start(ServiceController.java:413)
     at sun.reflect.GeneratedMethodAccessor4.invoke(Unknown Source)
     at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
     at java.lang.reflect.Method.invoke(Unknown Source)
     at org.jboss.mx.capability.ReflectedMBeanDispatcher.invoke(ReflectedMBeanDispatcher.java:284)
     at org.jboss.mx.server.MBeanServerImpl.invoke(MBeanServerImpl.java:517)
     at org.jboss.util.jmx.MBeanProxy.invoke(MBeanProxy.java:174)
     at $Proxy2.start(Unknown Source)
     at org.jboss.deployment.SARDeployer.start(SARDeployer.java:232)
     at org.jboss.deployment.MainDeployer.start(MainDeployer.java:814)
     at org.jboss.deployment.MainDeployer.deploy(MainDeployer.java:627)
     at org.jboss.deployment.MainDeployer.deploy(MainDeployer.java:591)
     at org.jboss.deployment.MainDeployer.deploy(MainDeployer.java:575)
     at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
     at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
     at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
     at java.lang.reflect.Method.invoke(Unknown Source)
     at org.jboss.mx.capability.ReflectedMBeanDispatcher.invoke(ReflectedMBeanDispatcher.java:284)
     at org.jboss.mx.server.MBeanServerImpl.invoke(MBeanServerImpl.java:517)
     at org.jboss.system.server.ServerImpl.doStart(ServerImpl.java:324)
     at org.jboss.system.server.ServerImpl.start(ServerImpl.java:221)
     at org.jboss.Main.boot(Main.java:148)
     at org.jboss.Main$1.run(Main.java:381)
     at java.lang.Thread.run(Unknown Source)
Caused by: java.sql.SQLException: Unexpected token: BINARY in statement [CREATE TABLE MLMEMBER (email VARCHAR(250) BINARY NOT NULL, name VARCHAR(250) BINARY, CONSTRAINT PK_MLMEMBER PRIMARY KEY (email))]
     at org.hsqldb.Trace.getError(Trace.java:180)
     at org.hsqldb.Result.<init>(Result.java:175)
     at org.hsqldb.jdbcConnection.executeHSQL(jdbcConnection.java:907)
     at org.hsqldb.jdbcConnection.execute(jdbcConnection.java:718)
     at org.hsqldb.jdbcStatement.fetchResult(jdbcStatement.java:686)
     at org.hsqldb.jdbcStatement.executeUpdate(jdbcStatement.java:85)
     at org.jboss.resource.adapter.jdbc.WrappedStatement.executeUpdate(WrappedStatement.java:231)
     at org.jboss.ejb.plugins.cmp.jdbc.JDBCStartCommand.createTable(JDBCStartCommand.java:166)
I don't know how to solve it.plz help me!

Try to check datasource config in JBoss.
Ex fo MYSQL same for other : To use the MySQL data source, copy /docs/examples/jca/mysql-ds.xml to the /server/default/deploy directory. Modify the mysql-ds.xml configuration file by setting to com.mysql.jdbc.Driver and to jdbc:mysql:///, where is the MySQL host server and is the MySQL database.
or check jbosscmp-jdbc.xml in your application
Ex :
<defaults>
<datasource>java:/MySqlDS</datasource>
<datasource-mapping>mySQL</datasource-mapping>
</defaults>

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    private JComboBox getJComboBoxNumOfSteps() {
           if (jComboBoxNumOfSteps == null) {
         String[] valStrings = { "1", "2", "3", "4", "5", "6", "7", "8", "9" ,"10","11","12","13","14","15","16","17"};
         jComboBoxNumOfSteps = new JComboBox(valStrings);
         jComboBoxNumOfSteps.setPreferredSize(new java.awt.Dimension(80,25));
         jComboBoxNumOfSteps.addActionListener(new java.awt.event.ActionListener() {
         public void actionPerformed(java.awt.event.ActionEvent e) {
                                              Integer i = new Integer(jComboBoxNumOfSteps.getSelectedIndex()+1);
                              jTextArea.append(i.toString());
              jTextArea.append("\n");
            return jComboBoxNumOfSteps;
    }Thanx Amar

    Depends what context, and who's exception....
    I'll go with my best guess here though.
    You're using wait() and notify() and or notifyAll() with some threads. In this case the IllegalStateException is being thrown because you are calling one of these methods on an object you are not holding the lock for. Here are some good resources.
    Doug Lea's site.
    http://g.cs.oswego.edu
    and the book
    http://java.sun.com/docs/books/cp/
    if not,.... oh well, describe your problem better.
    -Spinoza

  • ERROR: CPU RED-State Exception Reset Recovery

    Installed the latest released firmware patch 119244-03 to a Sunfire V880. Now the system is in a continuous loop. The error message can only be viewed via a RSC. There is no way to break the loop and the OBP password has been altered by this, thus no way going through this ideal unless there is some other OBP password that I am not aware of when this firmware is placed on.
    If anyone has any suggestions, please provide them before I kick the living #$#! out of this system.
    Thanks!
    Below is a clip from the RSC session:
    Done
    0:0>Full CPU Test.....
    Done
    0:0>Memory Block.....Done
    0:0>IO-Bridge Tests.....Done
    0:0>Full Memory Test.....Done
    0:0>Enable Errors.....Done
    0:0>INFO:
    0:0>     POST Passed all devices.
    0:0>POST:     Return to OBP.
    POST Reset
    Enabling system bus....... Done
    Probing Memory............ Done
    Initializing CPUs......... Done
    Initializing boot memory.. Done
    Initializing OpenBoot
    Probing system devices
    Probing I/O buses
    ERROR: CPU2 RED State Exception
    ERROR: CPU2 Second fault; CPU will be offlined.
    System State (CPU2 reporting)
    BBC Devices: 0000.0000.0000.0005 0000.0000.0000.0000
    BBC Arb: 0000.0000.0000.000f 0000.0000.0000.000f
    BBC Quiesce: 0000.0000.0000.0009 0000.0000.0000.000c
    BBC WDogAct: 0000.0000.0000.0001 0000.0000.0000.0001
    BBC POR Gen: 0000.0000.0000.0000 0000.0000.0000.0000
    BBC XIR Gen: 0000.0000.0000.0000 0000.0000.0000.0000
    BBC POR Src: 0000.0000.0000.0000 0000.0000.0000.0000
    BBC XIR Src: 0000.0000.0000.000b 0000.0000.0000.000f
    BBC EBus TC: 014f.99fd.a7e6.3f29 014f.99fd.a7e6.3f29
    CPU0 Config/Control/Status registers:
    CPUVersion: 003e.0014.5400.0507
    SafConfig: 0caa.01bc.0000.8002 5:1 ID:0 HBM TOL:15
    SafBaseAdr: 0000.0400.0000.0000
    DispatchCtl: 0000.0000.0000.0009 MS SI
    DCacheCtl: 0000.0200.0000.0000 WE
    ECacheCtl: 0000.0000.0009.4400 3:1 8MB mode=3-3-3 R/W-turn:2 ECC:on
    ErrorEnable: 0000.0000.0000.000b CEEN NCEEN UCEEN
    AFAR: 0000.0000.0000.0000
    AFSR: 0000.0000.0000.0000 (no errors set)
    DMMU SFAR: 0000.0000.fff7.90c0
    DMMU SFSR: 0000.0000.0080.8008 TM PR
    IMMU SFSR: 0000.0000.0000.0000 (no status set)
    CPU0 Trap registers: Trap Level = 1
    *TL=1 TT:     0000.0000.0000.0003
    TSTATE: 0000.0099.5800.1600 XCC:NC ICC:NC MM=TSO PEF PRIV IE
    TPC: 0000.0000.f004.fa80
    TnPC: 0000.0000.f004.fa84
    TL=2 TT: 0000.0000.0000.0068
    TSTATE: 0000.0099.5804.1400 XCC:NC ICC:NC MM=TSO PEF PRIV
    TPC: 0000.0000.f004.a2c0
    TnPC: 0000.0000.f004.a2c4
    TL=3 TT: 0000.0000.0000.0000
    TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
    TPC: 0000.0000.0000.0000
    TnPC: 0000.0000.0000.0000
    TL=4 TT: 0000.0000.0000.0000
    TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
    TPC: 0000.0000.0000.0000
    TnPC: 0000.0000.0000.0000
    TL=5 TT: 0000.0000.0000.0000
    TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
    TPC: 0000.0000.0000.0000
    TnPC: 0000.0000.0000.0000
    CPU0 General registers:
    %PIL: 15
    %PC: 0000.0000.f004.fa80
    %nPC: 0000.0000.f004.fa84
    %PSTATE: 0000.0000.0000.0035 MM=TSO AG
    %CCR: 0000.0000.0000.0099 XCC:NC ICC:NC
    %FPRS: 0000.0000.0000.0005 FEF DL
    %v0: 0000.0000.0000.0000 %v1: 0000.0000.0000.004a %v2: 0000.0000.0000.0000
    %v3: 0000.0000.fff7.8000 %v4: 0000.0000.0000.10e8 %v5: 0caa.01bc.0000.8002
    %v6: 0000.0000.0000.007f %v7: 0000.0000.0000.0134
    %m0: 0000.0000.0000.0000 %m1: 0000.0000.0000.000d %m2: 8000.00a0.ffbf.80b6
    %m3: 0000.0000.fff7.8000 %m4: 0000.0000.fff7.8000 %m5: ffff.fffc.003f.e000
    %m6: 8000.00a0.ffbe.a0b6 %m7: 0000.0000.0000.0001
    %a0: 0000.0000.0000.0000 %a1: 0000.07ff.f000.0000 %a2: 0000.0200.0000.0000
    %a3: ffff.ffff.f018.23b2 %a4: 0000.0000.0000.0000 %a5: 0000.0000.0000.0000
    %a6: 0000.0000.f000.dacc %a7: ffff.ffff.f001.fd8c
    %g0: 0000.0000.0000.0000 %g1: 0000.0000.ffff.ffff %g2: 0000.0000.f000.0000
    %g3: 0000.0000.fff7.8000 %g4: 0000.0000.0004.ff04 %g5: 0000.0000.f004.fb44
    %g6: 0000.0000.fef7.27f8 %g7: 0000.0000.fef7.1800
    %o0: 0000.0000.f000.00e0 %o1: 0000.0000.0000.0005 %o2: 0000.0000.0000.0004
    %o3: 0000.0000.f000.00e0 %o4: 0000.0000.0000.001f %o5: 0000.0000.0000.0000
    %o6: f000.0000.0000.c5f1 %o7: 0000.0000.f000.dacc
    %l0: 0000.0000.fef7.0000 %l1: 0000.0000.0000.4020 %l2: 0000.0000.0000.0021
    %l3: 0000.0000.0000.0011 %l4: 0000.0000.f004.6e48 %l5: 0000.0000.0000.0000
    %l6: 0000.07ff.fff8.0006 %l7: 0000.0000.07ff.fdc1
    %i0: ffff.ffff.ffff.ffff %i1: 0000.0000.0000.0000 %i2: 0000.0000.0000.0000
    %i3: 0000.0000.0000.0000 %i4: 0000.0000.0000.0000 %i5: 0000.0000.0000.0000
    %i6: 0000.0000.0000.0000 %i7: 0000.0000.0000.0000
    CPU0 Mem Ctrl registers:
    Mem Time Ctl1: 106e.9246.18a2.959a
    Mem Time Ctl2: 25c9.a82e.4a09.0020
    Mem Time Ctl3: 1050.04c9.24a2.82d0
    Mem Time Ctl4: 257d.382c.4a69.0020
    Mem Addr Dec1: 8000.7e02.8002.0000
    Mem Addr Dec2: 8000.7e02.8002.0200
    Mem Addr Dec3: 8000.7e02.8002.0400
    Mem Addr Dec4: 8000.7e02.8002.0600
    Mem Addr Ctl: 4904.1124.4221.1088
    CPU2 Config/Control/Status registers:
    CPUVersion: 003e.0014.5400.0507
    SafConfig: 1534.01bc.0004.8002 5:1 ID:2 HBM TOL:15
    SafBaseAdr: 0000.0400.0100.0000
    DispatchCtl: 0000.0000.0000.003b MS IFP SI RPE BPE
    DCacheCtl: 0000.0000.0000.0000
    ECacheCtl: 0000.0000.0009.4400 3:1 8MB mode=3-3-3 R/W-turn:2 ECC:on
    ErrorEnable: 0000.0000.0000.000b CEEN NCEEN UCEEN
    AFAR: 0000.07ff.ea00.2000
    AFSR: 0000.0000.0000.0000 (no errors set)
    DMMU SFAR: 0000.0000.fecd.a000
    DMMU SFSR: 0000.0000.0080.800c TM PR W
    IMMU SFSR: 0000.0000.0004.8028 TM CT1 PR
    CPU2 Trap registers: Trap Level = 5
    TL=1 TT: 0000.0000.0000.0064
    TSTATE: 0000.0088.1500.1600 XCC:N ICC:N MM=TSO PEF PRIV IE
    TPC: 0000.0000.f003.e124
    TnPC: 0000.0000.f003.e128
    TL=2 TT: 0000.0000.0000.0064
    TSTATE: 0000.0088.1504.1400 XCC:N ICC:N MM=TSO PEF PRIV
    TPC: 0000.0000.f000.0c80
    TnPC: 0000.0000.f000.0c84
    TL=3 TT: 0000.0000.0000.0064
    TSTATE: 0000.0088.1504.1400 XCC:N ICC:N MM=TSO PEF PRIV
    TPC: 0000.0000.f000.4c80
    TnPC: 0000.0000.f000.4c84
    TL=4 TT: 0000.0000.0000.0064
    TSTATE: 0000.0088.1504.1400 XCC:N ICC:N MM=TSO PEF PRIV
    TPC: 0000.0000.f000.4c80
    TnPC: 0000.0000.f000.4c84
    *TL=5 TT:     0000.0000.0000.0064
    TSTATE: 0000.0088.1504.1400 XCC:N ICC:N MM=TSO PEF PRIV
    TPC: 0000.0000.f000.4c80
    TnPC: 0000.0000.f000.4c84
    CPU2 General registers:
    %PIL: 13
    %PC: 0000.0000.f000.4c80
    %nPC: 0000.0000.f000.4c84
    %PSTATE: 0000.0000.0000.0434 MM=TSO AG
    %CCR: 0000.0000.0000.0080 XCC:N ICC:(clear)
    %FPRS: 0000.0000.0000.0006 FEF DU
    %v0: 0000.0000.0000.0000 %v1: 0000.0000.0000.0000 %v2: 0000.0000.0000.0000
    %v3: 0000.0000.0000.0000 %v4: ffff.ffff.0000.0000 %v5: 0000.0000.0000.0000
    %v6: 0000.0000.0000.0000 %v7: 0001.2000.0040.0000
    %m0: 0000.0000.0000.0000 %m1: 0000.0000.0000.06c0 %m2: 0000.0000.0000.0005
    %m3: 0000.0000.0000.0000 %m4: 0000.0000.0000.0000 %m5: 0000.0000.fef7.f000
    %m6: 0000.0000.f003.ca50 %m7: ffff.ffff.f002.02cc
    %a0: 0000.0000.0000.0000 %a1: 504f.5354.0000.0000 %a2: 0000.0200.0000.0000
    %a3: 0000.0000.fecd.a000 %a4: 0000.0000.fecd.a000 %a5: 0000.0000.fef7.f000
    %a6: 0000.0000.f003.ca50 %a7: ffff.ffff.f002.02cc
    %g0: 0000.0000.0000.0000 %g1: ffff.ffff.f017.7800 %g2: 0000.0000.f000.0000
    %g3: 0000.0000.fff7.8000 %g4: 0000.0000.f03f.c000 %g5: 0000.0000.f004.00dc
    %g6: 0000.0000.fef7.e6a0 %g7: 0000.0000.fef7.d7e8
    %o0: 0000.0000.0500.0000 %o1: 0000.0000.0007.fdf7 %o2: 0000.0000.0000.0000
    %o3: 0000.0000.f000.00e0 %o4: 0000.0000.0000.0000 %o5: 0000.0000.0000.0008
    %o6: 0000.0000.fff5.9701 %o7: 0000.0000.f003.ca50
    %l0: ffff.ffff.f172.6000 %l1: 0000.0000.0000.2000 %l2: 0000.0000.fecd.6000
    %l3: ffff.fffc.0000.0000 %l4: 0000.0000.0000.0007 %l5: 8000.00a0.ffb5.00b6
    %l6: 0000.0000.0000.0000 %l7: 0000.0000.f002.a4b8
    %i0: 0000.0000.0000.0000 %i1: 0000.0001.0000.0000 %i2: 0000.0000.0000.2710
    %i3: 0000.0000.0000.0004 %i4: 0000.0000.0000.0001 %i5: 0000.0000.0000.0000
    %i6: 0000.0000.0000.0000 %i7: 0000.0000.0000.0000
    CPU2 Mem Ctrl registers:
    Mem Time Ctl1: 106e.9246.18a2.959a
    Mem Time Ctl2: 25c9.a82e.4a09.0020
    Mem Time Ctl3: 1050.04c9.24a2.82d0
    Mem Time Ctl4: 257d.382c.4a69.0020
    Mem Addr Dec1: 8000.7e02.8002.0100
    Mem Addr Dec2: 8000.7e02.8002.0300
    Mem Addr Dec3: 8000.7e02.8002.0500
    Mem Addr Dec4: 8000.7e02.8002.0700
    Mem Addr Ctl: 4904.1124.4221.1088
    IO-Bridge 8 at 0000.0400.0400.0000
    Device ID fc00.0000.0011.a954
    Ctl/Stat 0255.5554.0080.7e02
    Error Ctl fc00.0000.0000.03e0
    Int Ctl 8000.0000.0000.0017
    Error Log 0000.0000.0000.0000
    ECC Ctl e000.0000.0000.0000
    EStar Ctl 0000.0000.0000.0001
    Queue Ctl 0000.0000.0000.0000
    Address Match Address Mask
    PCIA Mem 8000.07fd.0000.0000 0000.07ff.0000.0000
    PCIA C/IO 8000.07ff.ec00.0000 0000.07ff.fe00.0000
    PCIB Mem 8000.07fe.0000.0000 0000.07ff.0000.0000
    PCIB C/IO 8000.07ff.ee00.0000 0000.07ff.fe00.0000
    AFAR AFSR
    UE 0000.0000.0000.0000 0000.0000.0000.0000
    CE 0000.0000.0000.0000 0000.0000.0000.0000
    PCI A 0000.0000.0000.0000 0000.0000.0000.0000
    PCI B 0000.0000.0000.0000 0000.0000.0000.0000
    Control/Status Idle Check Diag Diagnostic
    PCI A 0000.0002.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
    PCI B 0000.0000.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
    IO-Bridge 9 at 0000.0400.0480.0000
    Device ID fc00.0000.0013.a954
    Ctl/Stat 0255.59a8.0090.7e02
    Error Ctl fc00.0000.0000.03e0
    Int Ctl 8000.0000.0000.0017
    Error Log 0000.0000.0000.0000
    ECC Ctl e000.0000.0000.0000
    EStar Ctl 0000.0000.0000.0001
    Queue Ctl 0000.0000.0000.0000
    Address Match Address Mask
    PCIA Mem 8000.07fb.0000.0000 0000.07ff.0000.0000
    PCIA C/IO 8000.07ff.e800.0000 0000.07ff.fe00.0000
    PCIB Mem 8000.07fc.0000.0000 0000.07ff.0000.0000
    PCIB C/IO 8000.07ff.ea00.0000 0000.07ff.fe00.0000
    AFAR AFSR
    UE 0000.0000.0000.0000 0000.0000.0000.0000
    CE 0000.0000.0000.0000 0000.0000.0000.0000
    PCI A 0000.0000.0000.0000 0000.0000.0000.0000
    PCI B 0000.0000.0000.0000 0000.0000.0000.0000
    Control/Status Idle Check Diag Diagnostic
    PCI A 0000.0002.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
    PCI B 0000.0000.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
    Resetting...
    ERROR: CPU RED-State Exception Reset Recovery
    FATAL: All CPUs failed or disabled! Attempting recovery...
    FATAL: All CPUs failed or disabled! Attempting recovery...
    Executing POST w/%o0 = 0000.0800.0101.4041
    0:0>
    0:0>@(#) Sun Fire[TM] V880/V890 POST 4.18.11 2006/05/03 07:51
    /export/delivery/delivery/4.18/4.18.11/post4.18.0/Camelot/daktari/integrated (root)
    0:0>Copyright � 2006 Sun Microsystems, Inc. All rights reserved
    SUN PROPRIETARY/CONFIDENTIAL.
    Use is subject to license terms.
    0:0>Jump from OBP->POST.
    0:0>Diag level set to MAX.
    0:0>Verbosity level set to NORMAL.
    0:0>
    0:0>Start selftest...
    0:0>CPUs present in system: 0:0 2:0
    0:0>Test CPU(s).....Done
    0:0>Init Scan/I2C.....Done
    0:0>Basic Memory Test.....Done
    0:0>Full CPU Test.....Done
    0:0>Memory Block.....Done
    0:0>IO-Bridge Tests.....Done
    0:0>Full Memory Test.....Done
    0:0>Enable Errors.....Done
    0:0>INFO:
    0:0>     POST Passed all devices.
    0:0>POST:     Return to OBP.
    POST Reset
    Enabling system bus....... Done
    Probing Memory............ Done
    Initializing CPUs......... Done
    Initializing boot memory.. Done
    Initializing OpenBoot
    Probing system devices
    Probing I/O buses
    ERROR: CPU2 RED State Exception
    ERROR: CPU2 Second fault; CPU will be offlined.
    System State (CPU2 reporting)
    BBC Devices: 0000.0000.0000.0005 0000.0000.0000.0000
    BBC Arb: 0000.0000.0000.000f 0000.0000.0000.000f
    BBC Quiesce: 0000.0000.0000.0009 0000.0000.0000.000c
    BBC WDogAct: 0000.0000.0000.0001 0000.0000.0000.0001
    BBC POR Gen: 0000.0000.0000.0000 0000.0000.0000.0000
    BBC XIR Gen: 0000.0000.0000.0000 0000.0000.0000.0000
    BBC POR Src: 0000.0000.0000.0000 0000.0000.0000.0000
    BBC XIR Src: 0000.0000.0000.000b 0000.0000.0000.000f
    BBC EBus TC: 014f.99fd.a7e6.3f29 014f.99fd.a7e6.3f29
    CPU0 Config/Control/Status registers:
    CPUVersion: 003e.0014.5400.0507
    SafConfig: 0caa.01bc.0000.8002 5:1 ID:0 HBM TOL:15
    SafBaseAdr: 0000.0400.0000.0000
    DispatchCtl: 0000.0000.0000.0009 MS SI
    DCacheCtl: 0000.0200.0000.0000 WE
    ECacheCtl: 0000.0000.0009.4400 3:1 8MB mode=3-3-3 R/W-turn:2 ECC:on
    ErrorEnable: 0000.0000.0000.000b CEEN NCEEN UCEEN
    AFAR: 0000.0000.0000.0000
    AFSR: 0000.0000.0000.0000 (no errors set)
    DMMU SFAR: 0000.0000.fff7.90c0
    DMMU SFSR: 0000.0000.0080.8008 TM PR
    IMMU SFSR: 0000.0000.0000.0000 (no status set)
    CPU0 Trap registers: Trap Level = 1
    *TL=1 TT:     0000.0000.0000.0003
    TSTATE: 0000.0099.5800.1600 XCC:NC ICC:NC MM=TSO PEF PRIV IE
    TPC: 0000.0000.f004.fa80
    TnPC: 0000.0000.f004.fa84
    TL=2 TT: 0000.0000.0000.0068
    TSTATE: 0000.0099.5804.1400 XCC:NC ICC:NC MM=TSO PEF PRIV
    TPC: 0000.0000.f004.a2c0
    TnPC: 0000.0000.f004.a2c4
    TL=3 TT: 0000.0000.0000.0000
    TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
    TPC: 0000.0000.0000.0000
    TnPC: 0000.0000.0000.0000
    TL=4 TT: 0000.0000.0000.0000
    TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
    TPC: 0000.0000.0000.0000
    TnPC: 0000.0000.0000.0000
    TL=5 TT: 0000.0000.0000.0000
    TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
    TPC: 0000.0000.0000.0000
    TnPC: 0000.0000.0000.0000
    CPU0 General registers:
    %PIL: 15
    %PC: 0000.0000.f004.fa80
    %nPC: 0000.0000.f004.fa84
    %PSTATE: 0000.0000.0000.0035 MM=TSO AG
    %CCR: 0000.0000.0000.0099 XCC:NC ICC:NC
    %FPRS: 0000.0000.0000.0005 FEF DL
    %v0: 0000.0000.0000.0000 %v1: 0000.0000.0000.004a %v2: 0000.0000.0000.0000
    %v3: 0000.0000.fff7.8000 %v4: 0000.0000.0000.10e8 %v5: 0caa.01bc.0000.8002
    %v6: 0000.0000.0000.007f %v7: 0000.0000.0000.0134
    %m0: 0000.0000.0000.0000 %m1: 0000.0000.0000.000d %m2: 8000.00a0.ffbf.80b6
    %m3: 0000.0000.fff7.8000 %m4: 0000.0000.fff7.8000 %m5: ffff.fffc.003f.e000
    %m6: 8000.00a0.ffbe.a0b6 %m7: 0000.0000.0000.0001
    %a0: 0000.0000.0000.0000 %a1: 0000.07ff.f000.0000 %a2: 0000.0200.0000.0000
    %a3: ffff.ffff.f018.23b2 %a4: 0000.0000.0000.0000 %a5: 0000.0000.0000.0000
    %a6: 0000.0000.f000.dacc %a7: ffff.ffff.f001.fd8c
    %g0: 0000.0000.0000.0000 %g1: 0000.0000.ffff.ffff %g2: 0000.0000.f000.0000
    %g3: 0000.0000.fff7.8000 %g4: 0000.0000.0004.ff04 %g5: 0000.0000.f004.fb44
    %g6: 0000.0000.fef7.27f8 %g7: 0000.0000.fef7.1800
    %o0: 0000.0000.f000.00e0 %o1: 0000.0000.0000.0005 %o2: 0000.0000.0000.0004
    %o3: 0000.0000.f000.00e0 %o4: 0000.0000.0000.001f %o5: 0000.0000.0000.0000
    %o6: f000.0000.0000.c5f1 %o7: 0000.0000.f000.dacc
    %l0: 0000.0000.fef7.0000 %l1: 0000.0000.0000.4020 %l2: 0000.0000.0000.0021
    %l3: 0000.0000.0000.0011 %l4: 0000.0000.f004.6e48 %l5: 0000.0000.0000.0000
    %l6: 0000.07ff.fff8.0006 %l7: 0000.0000.07ff.fdc1
    %i0: ffff.ffff.ffff.ffff %i1: 0000.0000.0000.0000 %i2: 0000.0000.0000.0000
    %i3: 0000.0000.0000.0000 %i4: 0000.0000.0000.0000 %i5: 0000.0000.0000.0000
    %i6: 0000.0000.0000.0000 %i7: 0000.0000.0000.0000
    CPU0 Mem Ctrl registers:
    Mem Time Ctl1: 106e.9246.18a2.959a
    Mem Time Ctl2: 25c9.a82e.4a09.0020
    Mem Time Ctl3: 1050.04c9.24a2.82d0
    Mem Time Ctl4: 257d.382c.4a69.0020
    Mem Addr Dec1: 8000.7e02.8002.0000
    Mem Addr Dec2: 8000.7e02.8002.0200
    Mem Addr Dec3: 8000.7e02.8002.0400
    Mem Addr Dec4: 8000.7e02.8002.0600
    Mem Addr Ctl: 4904.1124.4221.1088
    CPU2 Config/Control/Status registers:
    CPUVersion: 003e.0014.5400.0507
    SafConfig: 1534.01bc.0004.8002 5:1 ID:2 HBM TOL:15
    SafBaseAdr: 0000.0400.0100.0000
    DispatchCtl: 0000.0000.0000.003b MS IFP SI RPE BPE
    DCacheCtl: 0000.0000.0000.0000
    ECacheCtl: 0000.0000.0009.4400 3:1 8MB mode=3-3-3 R/W-turn:2 ECC:on
    ErrorEnable: 0000.0000.0000.000b CEEN NCEEN UCEEN
    AFAR: 0000.07ff.ea00.2000
    AFSR: 0000.0000.0000.0000 (no errors set)
    DMMU SFAR: 0000.0000.fecd.a000
    DMMU SFSR: 0000.0000.0080.800c TM PR W
    IMMU SFSR: 0000.0000.0004.8028 TM CT1 PR
    CPU2 Trap registers: Trap Level = 5
    TL=1 TT: 0000.0000.0000.0064
    TSTATE: 0000.0088.1500.1600 XCC:N ICC:N MM=TSO PEF PRIV IE
    TPC: 0000.0000.f003.e124
    TnPC: 0000.0000.f003.e128
    TL=2 TT: 0000.0000.0000.0064
    TSTATE: 0000.0088.1504.1400 XCC:N ICC:N MM=TSO PEF PRIV
    TPC: 0000.0000.f000.0c80
    TnPC: 0000.0000.f000.0c84
    TL=3 TT: 0000.0000.0000.0064
    TSTATE: 0000.0088.1504.1400 XCC:N ICC:N MM=TSO PEF PRIV
    TPC: 0000.0000.f000.4c80
    TnPC: 0000.0000.f000.4c84
    TL=4 TT: 0000.0000.0000.0064
    TSTATE: 0000.0088.1504.1400 XCC:N ICC:N MM=TSO PEF PRIV
    TPC: 0000.0000.f000.4c80
    TnPC: 0000.0000.f000.4c84
    *TL=5 TT:     0000.0000.0000.0064
    TSTATE: 0000.0088.1504.1400 XCC:N ICC:N MM=TSO PEF PRIV
    TPC: 0000.0000.f000.4c80
    TnPC: 0000.0000.f000.4c84
    CPU2 General registers:
    %PIL: 13
    %PC: 0000.0000.f000.4c80
    %nPC: 0000.0000.f000.4c84
    %PSTATE: 0000.0000.0000.0434 MM=TSO AG
    %CCR: 0000.0000.0000.0080 XCC:N ICC:(clear)
    %FPRS: 0000.0000.0000.0006 FEF DU
    %v0: 0000.0000.0000.0000 %v1: 0000.0000.0000.0000 %v2: 0000.0000.0000.0000
    %v3: 0000.0000.0000.0000 %v4: ffff.ffff.0000.0000 %v5: 0000.0000.0000.0000
    %v6: 0000.0000.0000.0000 %v7: 0001.2000.0040.0000
    %m0: 0000.0000.0000.0000 %m1: 0000.0000.0000.06c0 %m2: 0000.0000.0000.0005
    %m3: 0000.0000.0000.0000 %m4: 0000.0000.0000.0000 %m5: 0000.0000.fef7.f000
    %m6: 0000.0000.f003.ca50 %m7: ffff.ffff.f002.02cc
    %a0: 0000.0000.0000.0000 %a1: 504f.5354.0000.0000 %a2: 0000.0200.0000.0000
    %a3: 0000.0000.fecd.a000 %a4: 0000.0000.fecd.a000 %a5: 0000.0000.fef7.f000
    %a6: 0000.0000.f003.ca50 %a7: ffff.ffff.f002.02cc
    %g0: 0000.0000.0000.0000 %g1: ffff.ffff.f017.7800 %g2: 0000.0000.f000.0000
    %g3: 0000.0000.fff7.8000 %g4: 0000.0000.f03f.c000 %g5: 0000.0000.f004.00dc
    %g6: 0000.0000.fef7.e6a0 %g7: 0000.0000.fef7.d7e8
    %o0: 0000.0000.0500.0000 %o1: 0000.0000.0007.fdf7 %o2: 0000.0000.0000.0000
    %o3: 0000.0000.f000.00e0 %o4: 0000.0000.0000.0000 %o5: 0000.0000.0000.0008
    %o6: 0000.0000.fff5.9701 %o7: 0000.0000.f003.ca50
    %l0: ffff.ffff.f172.6000 %l1: 0000.0000.0000.2000 %l2: 0000.0000.fecd.6000
    %l3: ffff.fffc.0000.0000 %l4: 0000.0000.0000.0007 %l5: 8000.00a0.ffb5.00b6
    %l6: 0000.0000.0000.0000 %l7: 0000.0000.f002.a4b8
    %i0: 0000.0000.0000.0000 %i1: 0000.0001.0000.0000 %i2: 0000.0000.0000.2710
    %i3: 0000.0000.0000.0004 %i4: 0000.0000.0000.0001 %i5: 0000.0000.0000.0000
    %i6: 0000.0000.0000.0000 %i7: 0000.0000.0000.0000
    CPU2 Mem Ctrl registers:
    Mem Time Ctl1: 106e.9246.18a2.959a
    Mem Time Ctl2: 25c9.a82e.4a09.0020
    Mem Time Ctl3: 1050.04c9.24a2.82d0
    Mem Time Ctl4: 257d.382c.4a69.0020
    Mem Addr Dec1: 8000.7e02.8002.0100
    Mem Addr Dec2: 8000.7e02.8002.0300
    Mem Addr Dec3: 8000.7e02.8002.0500
    Mem Addr Dec4: 8000.7e02.8002.0700
    Mem Addr Ctl: 4904.1124.4221.1088
    IO-Bridge 8 at 0000.0400.0400.0000
    Device ID fc00.0000.0011.a954
    Ctl/Stat 0255.5554.0080.7e02
    Error Ctl fc00.0000.0000.03e0
    Int Ctl 8000.0000.0000.0017
    Error Log 0000.0000.0000.0000
    ECC Ctl e000.0000.0000.0000
    EStar Ctl 0000.0000.0000.0001
    Queue Ctl 0000.0000.0000.0000
    Address Match Address Mask
    PCIA Mem 8000.07fd.0000.0000 0000.07ff.0000.0000
    PCIA C/IO 8000.07ff.ec00.0000 0000.07ff.fe00.0000
    PCIB Mem 8000.07fe.0000.0000 0000.07ff.0000.0000
    PCIB C/IO 8000.07ff.ee00.0000 0000.07ff.fe00.0000
    AFAR AFSR
    UE 0000.0000.0000.0000 0000.0000.0000.0000
    CE 0000.0000.0000.0000 0000.0000.0000.0000
    PCI A 0000.0000.0000.0000 0000.0000.0000.0000
    PCI B 0000.0000.0000.0000 0000.0000.0000.0000
    Control/Status Idle Check Diag Diagnostic
    PCI A 0000.0002.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
    PCI B 0000.0000.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
    IO-Bridge 9 at 0000.0400.0480.0000
    Device ID fc00.0000.0013.a954
    Ctl/Stat 0255.59a8.0090.7e02
    Error Ctl fc00.0000.0000.03e0
    Int Ctl 8000.0000.0000.0017
    Error Log 0000.0000.0000.0000
    ECC Ctl e000.0000.0000.0000
    EStar Ctl 0000.0000.0000.0001
    Queue Ctl 0000.0000.0000.0000
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    PCIA Mem 8000.07fb.0000.0000 0000.07ff.0000.0000
    PCIA C/IO 8000.07ff.e800.0000 0000.07ff.fe00.0000
    PCIB Mem 8000.07fc.0000.0000 0000.07ff.0000.0000
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    <!--context-param>
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    <param-value>false</param-value>
    </context-param>
    <!-- Faces Filter -->
    <filter>
    <filter-name>faces</filter-name>
    <filter-class>oracle.adfinternal.view.faces.webapp.FacesFilter</filter-class>
    <init-param>
    <param-name>faces-servlet-url-pattern</param-name>
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    </filter>
    <filter>
    <filter-name>adfFaces</filter-name>
    <filter-class>oracle.adf.view.faces.webapp.AdfFacesFilter</filter-class>
    </filter>
    <!-- Faces Filter Mappings -->
    <filter-mapping>
    <filter-name>faces</filter-name>
    <url-pattern>*.jspx</url-pattern>
    </filter-mapping>
    <filter-mapping>
    <filter-name>adfFaces</filter-name>
    <servlet-name>facesS</servlet-name>
    </filter-mapping>
    <!-- Faces Servlet -->
    <servlet>
    <servlet-name>facesS</servlet-name>
    <servlet-class>javax.faces.webapp.FacesServlet</servlet-class>
    </servlet>
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    <!--servlet>
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    <servlet-class>oracle.jsp.runtimev2.JspServlet</servlet-class>
    <init-param>
    <param-name>tags_reuse_default</param-name>
    <param-value>none</param-value>
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    </servlet-->
    <!-- Faces Servlet Mappings -->
    <servlet-mapping>
    <servlet-name>facesS</servlet-name>
    <url-pattern>/faces/*</url-pattern>
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    <!-- Welcome Files -->
    <welcome-file-list>
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    <!-- ADF Faces Tag Library -->
    <taglib>
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    <taglib-location>/WEB-INF/af.tld</taglib-location>
    </taglib>
    <taglib>
    <taglib-uri>http://xmlns.oracle.com/adf/faces/EA14/html</taglib-uri>
    <taglib-location>/WEB-INF/afh.tld</taglib-location>
    </taglib>
    <!-- Faces Core Tag Library -->
    <taglib>
    <taglib-uri>http://java.sun.com/jsf/core</taglib-uri>
    <taglib-location>/WEB-INF/jsf_core.tld</taglib-location>
    </taglib>
    <!-- Faces Html Basic Tag Library -->
    <taglib>
    <taglib-uri>http://java.sun.com/jsf/html</taglib-uri>
    <taglib-location>/WEB-INF/html_basic.tld</taglib-location>
    </taglib>
    <!-- Survey Demo (Custom) Tag Library -->
    <taglib>
    <taglib-uri>http://xmlns.oracle.com/adf/faces/EA14/demo</taglib-uri>
    <taglib-location>/WEB-INF/survey.tld</taglib-location>
    </taglib>
    <taglib>
    <taglib-uri>http://xmlns.oracle.com/adffacesdemo</taglib-uri>
    <taglib-location>/WEB-INF/uixdemo.tld</taglib-location>
    </taglib>
    </web-app>
    I use Tomcat 5.0.18 (embeded in Eclipse for web) and ADF Faces ea14 (with ea13 was the same problem.)
    Thanks for any hints...

    When I refresh the page after this exception, the content is displayed correctly. When I make new request on this page, I get new Illegal state exception, after the refresh the content is displayed correctly again ...

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