Cannot run Simulink dll at the same time as running real-time target VI

Question

Hello
What I am trying to do is run a model dll created in Simulink to control some servo's through a CompactRio 9014. 
At the moment I have managed to create three VIs
1) In the FPGA target that performs the PWM on a desired channel
2) That takes the value of a network variable which contains the position required and feeds that to the 1st VI
3) A VI that runs on the host computer that modifies the value of the network variable to change the position
I can get these three VIs working and the servo controlled, but when I try to update the value of the network variable using the simulation, by deploying the simulation to the RT target and running it, it says
'Access denied: This target is already in use by another project or host computer.'
I assume as this is because the project is already connected to the cRio, so I disconnect and am able to deploy the model files. 
However when I try to run one of the VIs in the RT Targer along with the simulation I get the error:
'This VI is downloaded on the target but is not present in the project you are attempting to deploy.  All VIs on the target will be closed unless you choose to add the missing VI to the project.'
With a large number of missing VIs...
Would I be doing this wrong, i.e. is there a much simplier way to control the FPGA inputs using the simulation, or is there something I could have missed?
Thanks
Geoff
Solved!
Go to Solution.

Answer 1

Hi Geoff,
It seems that you are on the right track except for some concepts that I
want to review:
A CompactRIO or cRIO has 3 different components:
1)     
Real-Time controller (in your case a 9014)
2)     
FPGA backplane (this could be a 9102, or a 9103, 910x,
etc)
3)     
I/O modules (like a 9401, 9263, etc)
When you write an application for cRIO you usually have three different VIs:
1)     
Host VI – This VI is used as a user interface and runs in
Windows (under “My Computer” in the LabVIEW project) This VI is optional because
you might want to run the cRIO headless.
2)     
RT VI – This is the VI that runs in the cRIO controller
(in your case the 9014).  This VI lives
under the cRIO target in your LabVIEW project. 
3)     
FPGA VI – This is the VI that runs in the cRIO
backplane like a 9102.  This lives under
the cRIO >> FPGA target in the LabVIEW project.
The ONE application that I was talking about in my last post is for the RT
VI.  There can only be one RT VI that
gets deployed.  If you want to run
multiple VIs in the cRIO RT, then you need to run those VIs as subVIs of one
top level VI.
LabVIEW Simulation Interface Toolkit (SIT) has a tool called the SIT
Connection Manager that creates two of these three VIs for you (the RT and the
Host VIs).
Please refer to the following link about the SIT Help.  Go to the How To section.  It is organized in a kind of step by step
tutorial.
http://zone.ni.com/reference/en-XX/help/371504D-01/
In your case it is going to be a bit more difficult because of two things:
One, you are using a VxWorks target. 
Two, you want to use your own FPGA VI.
Let’s address each one of them:
1)     
VxWorks target- To use the SIT Connection Manager you
need to use a DLL not an OUT file, even though you need the OUT file for the cRIO VxWorks target.  The reason is
that this tool needs to read the compiled model to know what the
parameters, signals, inports and outports of your model are.  Because the tool runs in Windows you cannot
open an OUT file (meant for a different OS) so you need to give it a DLL. 
For this reason you will need to compile your model file into an OUT
file and a DLL.  Once you give a DLL to
the Connection Manager and you select your cRIO as the execution target, keep
doing the rest of the steps as the help says. 
LabVIEW will identify that you are using a VxWorks target and will
download the OUT file to the cRIO.
2)     
Custom FPGA VI – LabVIEW SIT has some FPGA bitfiles
(compiled FPGA VIs) that it can use. 
When you open the SIT connection manager and go to the Hardware IO
mapping section it asks you to select the bitfile.  If you want, you can select one of the
shipping bitfiles but iIf you
want to use your own, then you will need to do some changes to your FPGA VI , recompile it and
save the bitfile in a specific location with a specific name.
Please refer to the following link for
instructions on how to create your custom FPGA VI:
http://zone.ni.com/reference/en-XX/help/371504D-01/lvsithowto/sit_h_custfpga/
What I would suggest is that you start with a very simple example and using
one of the shipping bitfiles.  Look into
the following path for a very simple Sine wave generation example:
C:\Program Files\National Instruments\LabVIEW 8.6\examples\Simulation
Interface\Sine Wave
Because you are running a VxWorks target you will need to recompile this
example model sinewave.mdl to an OUT file.
To get a better understanding of what SIT does you might
want to check some quick videos. Go to
http://sine.ni.com/nips/cds/view/p/lang/en/nid/11763  and under the
resources tab there are two videos called Demo - <something>...
Hope this helps and let me know if you have more questions.
Ricardo
National InstrumentsSystems Engineering