Clocking wizzard throws error while instantiating in IPI

Question

Dear community,
I am using the ZedBoard without the PS side. My Goal is to create a 50MHz clock for my logic. So I use the 100MHz PL clock (the ZedBoard provides a 100MHz clock at Zynq pin Y9).
To get the 50MHz I am trying to use a MMCM which I would like to create with the clocking wizard. Therefore I do the following steps in Vivado 14.4:
creating new rtl project without any design files and choosing the zedboard
create block design
add ip --> clocking wizard
Then the following error occurs without instantiating the clock wizard (list of tcl commands):
create_project clocking_wizard_test C:/Users/abcd/VHDL_Code/Vivado_Testground/clocking_wizard_test -part xc7z020clg484-1
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2014.4/data/ip'.
set_property board_part em.avnet.com:zed:part0:1.2 [current_project]
set_property target_language VHDL [current_project]
create_bd_design "design_1"
Wrote  : <C:/Users/abcd/VHDL_Code/Vivado_Testground/clocking_wizard_test/clocking_wizard_test.srcs/sources_1/bd/design_1/design_1.bd>
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 clk_wiz_0
ERROR: [#UNDEF] conversion to double from string is failed
unexpected "," outside function argument list
in expression "1000 / 10,000"
ERROR: [IP_Flow 19-3188] Error occurred while initializing 'clk_wiz_0'
Tcl error in update procedure while setting value 'MMCM' on the parameter 'PRIMITIVE'. unexpected "," outside function argument list
in expression "1000 / 10,000"
CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'design_1_clk_wiz_0_0'. Error during customization.
ERROR: [#UNDEF] Error occurred while initializing 'clk_wiz_0'
Tcl error in update procedure while setting value 'MMCM' on the parameter 'PRIMITIVE'. unexpected "," outside function argument list
in expression "1000 / 10,000"
ERROR: [BD 5-7] Error: running create_bd_cell.
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
endgroup
How can I fix it?

Answer 1

Thanks first of all for your replies.
Allright, now I got some results. Or in different words: I can reproduce a strange behavior regarding the clocking wizard:
Leave the system language (win7) set to German and changing just the decimal separator (,) with (.) it does not work.
When I got the error message (see initial thread) than I can work around with closing Vivado and reopen it. If I try to instantiate the MMCM with the clocking wizard after reloading Vivado then it works (without error or warning messages). I even can gernerate a bitstream. But everytime I open a synthesized or implemented design I get the above mentioned errors. If I delete the clocking wizard at the IPI and try to add a "new" one then Vivado refuses it again (at least until I close Vivado and reopen it again). With this method I would say it works almost ;-)
set the system language (win7) globally to US English it works. At least I wasn´t able to reproduce this error.
Is this issue planned to be fixed in the next version of Vivado?
Regards!