CRIO DMA FIFO transfer Issue-Voltage not coming to correct channels

Question

Hi All,
Using crio 9073 and NI 9205, I am transferring Data (Channel data type = FXP, Word length 37 bits, 16 bits and FIFO also same data type) from FPGA DMA (Requested No of elements configured in FPGA is 16383) To RT DMA (Requested number of elements in 32744)
FPGA notes:
Total channels =16 (Differential mode)
Loop time of FPGA =20 ms (Per read 20 samples from each channel, so 320 samples per iteration)
RT notes:
SCTL=running at 10 ms where DMA transfer happening do that check remaining elements and then do DMA as well.
Issue:
When I run the code in above scenario, whatever different voltages given to 4 channels (loop backed 9263 to 9205, fpga interactive mode and only giving 4 channels voltages now just for testing) and i do DMA in RT side, decimate the 320 data and i found Channel 0 voltage given in FPGA is not coming in 0 index of the decimated array in RT DMA read data, instead Channel 0 voltage is coming in Index 7 of the RT DMA read data.  Channel 1 coming at index 8...vice versa… Seems, some data shifting happening.
But in FPGA i could see correct differential voltage coming to correct channels (Ch 0 is 1.4 V ,FPGA indicator shows me correct voltage at index 0 a 1.4 and vice versa)..
Please suggest me why this is happening and what is best way i can get correct channel voltage data in RT based on my above conditions.

Answer 1

This is how I do where I need to only measure continuos analog values through FIFO. I don't use calibrated analog channel. I use raw analog channel and do calibration in host VI. I have attached screenshot of my code. I put 123456789 check sequence in build array function in FPGA VI.
If I want to read 2000 samples then I keep FIFO 4000 at host side.
I keep sample count in multiple of no. of channel. In my code build array has 3 element so I read 3*X. where X number of sample required per channel.
If you don't understand from code let me know.
PBP (CLAD)
Labview 6.1 - 2014
KUDOS ARE WELCOMED.
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Attachments:
FPGA VI.jpg ‏205 KB
FPGA 2.png ‏92 KB
Host VI.jpg ‏168 KB