CVS-1458RT - ISO I/P triggered timed loop

Hi everyone,
I am developing a real-time machine vision application on a CVS-1458 RT.
What I am aiming is a timed loop that is triggered via external clock (in my case a photoelectric sensor connected to an ISO input). All examples I can find are related to DAQmx devices, nothing related to visionRIO.
Question 1: Is this the best way to construct the acquisition loop? I want it to be condition based as to free-up the CPU from continous polling. If not, wht is the best way ?
Question 2: If the above method is OK, how can I setup the input node of my timed loop in a way to implement this ?
Thank you,
Omar

Hi Omar,
I was able to find some Vision-RIO examples in the Example Finder of LabVIEW. If you open LabVIEW and navigate to Help>> Find Examples.
In the Example Finder in the Browse tab navigate to Hardware Input and Output>> Vision Acquisition>> Vision-RIO.

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Missed iterations of TTL triggered timed loop

Hello everyone,
I have a camera control VI that waits for TTL information from the camera shutter and uses it as a timing source for a timed loop. In this timed loop the camera is readout and analyzed. The program should react as soon a possible to a new image and therefore I set the timed loop to 'Discard missed items' so that it doesnt try to catch up (the events im trying to detect are quite rare and last several frames).
The problem is this: When I set the camera for a certain numebr of frames (for example 10.000 frames) sometimes due to the discarded frames the loop iteration number never reaches the expected last frame number and doesnt exit (it stays at 9.998 for instance). I noticed I can prevent this by deselecting 'maintain original phase' . However it is unclear to me what exactly happens with these settings in a TTL triggered situation like this.
Is it the case that the loop skips the new data but starts the next loop at the correct iteration number (+1)? Or is something else happening?
Im thankfull for any help!
Solved!
Go to Solution.

Dear j.win,
If you deselect "Maintain Original Phase", actually you will never discard any iteration, whatever the value of "Discard missed items". Instead, the loop will try to catch up with the late iterations.
Using an external timing source (your TTL for example) instead of an internal timing source does not change anything. You can use the "Period" (dt) input of the Timed Loop to specify when the loop is supposed to iterate (the unit is the "ticks" in the case of an external timing source). A value of "1" means that the Loop try to iterate at every ticks of the external timing source. If for some reason one iteration lasts longer than that, you will have a "late iteration". Also with a value of "1", it is not possible to modify the "phase", then the "Maintain Original Phase" parameter will just defined wether or not you skip the iteration. If "Maintain Original Phase" is false, the loop will execute immediatly after a late iteration to still execute it, but a bit latter. If the "Maintain Original Phase" is true, the loop will execute immediatly after a late iteraion if the "Discard missed item" is false otherwise the loop will skip the iteration.
Is it clearer now?
Regards,
Cédric | NI Belgium

Boolean triggered timed loop

Good afternoon Labview board,
I'm building code that turns a mouse click into a 2sec boolean true (indicator). My requirements are that...
1. Once the 2sec passes the boolean switches back to false.
2. The user is unable to re-trigger the process until it returns false.
I have attached a LabView v8.6 VI. It works, but very poorly. It often misses the mouse click, and has an unwanted latency.
Any help improving or redesigning it would greatly appreciated!
Thanks,
super-neuron
Attachments:
Untitled 2.vi ‏21 KB

Hi Super,
Have modified a VI i used a while back to do something similar:
I have made this into a subvi so you can use it as shown below:
I have attached both the subvi and example vi below in 8.6.
Hope it is what you need.
Regards,
Lucither
"Everything should be made as simple as possible but no simpler"
Attachments:
Timed True Latch.vi ‏38 KB
Timed True Latch Example.vi ‏7 KB

LabVIEW RT, Timed loop, finished late, Call by reference

I have a timed loop triggered by the sample clock of a DAQ-Card. The sample Clock is 8 kHz and the loop will run with dt = 4. Normally the loop is running without finished late[i-1]. But from time to time it happens that the loop is running extremly longer which means instead of 0.5 millisec it needs 4 - 5 millisec. It seems this doesn't never occur while accessing DAQmx.
The application uses plugin technologies and some of the VIs in the timed loop are preloaded and called by Call by Reference.
Does those VIs inherit the priority, execution system and CPU of the timed loop?
The application is running on LV RT 2009 on a Dual core PXI-Controller. The timed loop is bound to CPU 1. There is no difference runinng the application from the development environment or as a startup application.
For the measuring test I modified the application in a way that I don't have:
disk access for storing the result file
TCP/IP communication
Controls on the front panel of the top level VI
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

To keep you informed:
I stripped the application and have left only the measurement storing module and the timed loop. The loop was using the microsecond timer running each 500 µsec. Additional all Non-Real-Time modules were loaded and only one module creates a XML string and sends it to the communication layer which will drop it because no TCP/IP port is open. The creation of the XML string is done each 300 ms.
In this case I don't have any finished late iterations
Next I added the DAQ Module. Now I get finished late again but with a lesser frequency as original.
I removed all unnesseccary tasks from the DAQ moulde leaving one task for a PXI-4204 for using as the clock source for the timed loop. No I get finished late seldom.
I removed the module which will send the XML string and I don't get finished late.
Next I was adding code to see memory allocation. I can when memory allocation is changing but it is not related to the finished late iterations.
Next time I have the chance to do more tests I will see which DAQ task triggers the finished late iterations. I have one AI task on a PXI-4204, 4 Counter tasks on a PXI-6602, 1 DI task on a PXI-6514, 1 DO task on a PXI-6514, 1 DI task on a PXI-6259, 1 DO task on a PXI-6259, 1 AO task on a PXI-6259 and 1 AO task on a PXI-6711.
The AI task on the PXI-4204 is running in Continous Sampling (Single Point HW Timed is not supported), all other tasks exept the DI and DO are Single Point HW Timed.
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

Timed loop and CPU usage

Platform is WIN_XP Pro and machine is a P4 at 2.5Ghz with 512 Mb ram.
LV7.1 + PCI 6229
I am using 50ms Timed loop for running a state machine inside it
and also a whole lot of other things like reading / writing
DAQMx functions; file I/O functions and such. As the
project involves a main and sub-panlel set up local variables
could not be elimnated fully and there should be something like 150 of
them. But not all are accessed always - maybe about 15 of them at any
given time depending on the SM staus.
Problem :
Once started the "Finished late" indication is off and
the actual timing alternates between 49 to 52 ms. The CPU
usage is around 25%.
But as time goes by, the system gets unstable : After 15 minutes
or so, the Finished Late indication is always ON and the CPU usage is
gradually tending towards or exceeds 100%.
Obviously the machine control timing now gets affected and things slow
down badly. Closing the application ands restarting repeats the above
cycle.
I am at a loss to understand what is happening ? WIll
breaking down the single Timed Loop to multiple ones help ? WIll
that be an efficient way of parallel threading ?
I can post the code but its quite large and will do it as a last resort.
thanks
Raghunathan
Raghunathan
LV2012 to Automate Hydraulic Test rigs.

Hello,
It sounds like an interesting problem. It would be worth some experimentation to figure out what's going wrong - attempting to decouple major "pieces" of the code would be helpful. For example, you could try breaking your code into multiple loops if that makes sense in your architecture, but perhaps you could even eliminate all but one of the loops to begin with, and see if you can correlate the problem to the code in just one of your loops.
Another concern is that you mention using many local variables. Variable read operations cause new buffer allocations, so if you're passing arrays around that way, you could be hitting a problem of forcing your machine to perform many allocations and deallocations of memory. As arrays grow, this can be a bigger and bigger problem. You can use other techniques for passing data around your block diagram, such as dataflow if possible (just simple wires), or queues where dataflow can't dicatate program flow completely.
Hopefully looking into your code with the above considerations will lead you in the right direction. In your case, removing code so that you can identify which elements are causing the problem should help significantly.
Best Regards,
JLS
Best,
JLS
Sixclear

Logc 7.1 drops when triggering MIDI loops?

I have an Akai sampler, and when i trigger loops within logic 7 via midi, at the end of every bar the Logic stops the loop short of the bar?
So if i do a 4 bar loop the re-triggering is fine until it comes around to loop back to the start again?!? where it jumps?
This is fine on my G5 OSX with 4Gb , triggering the loops on ableton or Protools, only with Logic?!
Any ideas?

update:
Apple technician told me the way Logic uses cores changes depending on it's application.... ugh

Questions about parallel and series sturcture in SCTL (single clock timed loop) in FPGA VI

I am using LV 8.2.
I have wriiten a FPGA VI, in this VI, there are 3 filters inside the SCTL (single clock timed loop) (I use the shift register to be the effect of unit delay). Would I save the resources of the FPGA used (such as slices and LUT) in the compliation report if I use 3 SCTL ( 1 SCTL contain 1 filter) and cascade them in series?
Thank you!

Sorry, I am afraid that you have misunderstood my meaning.
Here is the method you suggested before:
I mean I use the shift registers attached in the while loop, not in the SCTL. The number of shift registers used will not be decreased when we increase the number of SCTL in the second plate of the flat sequence structure. Totally , there are 6 pairs shift registers for 3 filters (1 filter needs 2 pairs). I mean I put the calculation parts, such as b0*x[n]+b1*x[n-1]+b2*x[n-2] inside the SCTL ( the operations of multiplication and add). Instead of putting 3 filters numeric operation part in one SCTL. will we reduce the resources used if we use 1 SCTL to do the operation parts of 1 filter? As the code inside each SCTL will be reduced.
Maybe you tell me if such approach will reduce the reosources used? Or there is no difference?
Thank you!

Can I run a fast timed loop?

It appears that a timed loop cannot run faster than 100 hz. In other words, the "period" input for a timed loop cannot be less than 10. Is this true? I am using the Elapsed Time VI to measure time increments. The time increments output from this VI are at least 0.01 secs regardless of how fast I attempt to run the time loop. Perhaps the limitation lies in the Elapsed Time VI, not in the Timed Loop. Should I try a different approach to measuring the delta time between iterations of a time loop? TIA.
-jlivermore

Here's the simple way to measure loop timing:
Actually, what else is running in your loop (e.g. property nodes, DAQ, etc.)? Can you show us your code? What is your LabVIEW version?
Message Edited by altenbach on 09-29-2008 11:22 AM
LabVIEW Champion . Do more with less code and in less time .
Attachments:
MeasureLoopTiming.PNG ‏7 KB

Using timer/counter with PCI-6221/USB-6210 to control timed-loop VI

Dear all,
I need to ask about two devices and one of their functionalities, PCI-6221 and USB-6210. For our NI-based system, we need to control some timings in a Timed-Loop vi, for that currently we are using PCI-6221 and we give external TTL signal (at 1 kHz) to it,
recenntly we need to make some changes and for that we found USB 6210 DAQ to be more suitable, but we need to clear ourselves on some specific things.
Can the counter/timers functions available in the either PCI 6221 or USB 6210 can be used to control the Timed-loop VI by giving external clock or by using their own internal clock source?
Although we are using external clock with the PCI 6221 but we want to know about the usage of their internal clock, also are controlling timed-loop also possible for USB-6210
Also... What if we use the RTOS, are they still able to control the timed-loop VI without giving any 'EXTERNAL CLOCK' and using the internal clock sources of the DAQs
Waiting for reply,
Bests,
RaJaf
Solved!
Go to Solution.

Ben,
I having read previous email which I send earlier with general overview, we discussed in more detail within our team and I am giviing the specific answers.
Please check in RED the most recent answers. Blue are the questions/suggestions by your side.
1.    Using Internal hardware clock of PCI-6221 would enable us get rid of external clock, but how to divert the internal hardware clock to the current settings. Any idea (can you provide us with some reference manul for otherwise). I mean is there some flag-bit etc. or VI
2.       Is it also meant that with the installation of RTOS the timed-loop can directly get the timing source from the internal hardware clock PCI-6221? --- How???
3.       In order to make desktop to work as RT system, what is the hardware (motherboard, processor, etc..) requirement? What are the LabVIEW modules (specific name) that needed to be installed? Our platform is LabVIEW 8.6. (Currently we have windows-7 with i7 core processor)
What kind of application are you intending for this system? ---- high-speed laser scanning system.
Are you most concerned about accuracy, speed, or responsiveness? To control the laser mirror scanner to move at 1 kHz or 2 kHz speed. On the other hands, using PCI-5105 (128 MB memory) as a DAQ for real-time/on-the-fly data processing.
Bests,
RAJAF

Timed Loop in Producer/Consumer Loop

Hello!
I have a producer/consumer loop LabVIEW program setup to allow me to properly capture images that are quite large (8MP) at approximately 14 frames per second (FPS). The program works great when the consumer loop is a 'while loop' (records at 14fps no problem), but I wanted to make it into a timed loop, so that I may vary the FPS as required. An oddity arises when I do this. Anywhere below 12fps, the loop works fine and the data is recorded properly. However, when I bump it up to 13fps, the consumer calculated FPS goes haywire and starts jumping between ~9 and ~13fps (data processing gets bogged?). When I set the required FPS to 14, the loop executes at a steady 7FPS maximum. Is there something I can do to rectify this situation?
I have attached my .VI
Thanks in advance!
Solved!
Go to Solution.
Attachments:
ProcessSplitJPG-FPS.vi ‏100 KB

Palanski,
Are you using LabVIEW Real-Time? Timed loops in a windows OS don't really increase determinism more than a while loop with a wait until next multiple timer. Before you changed the producer consumer loop to include a while loop was the programming running correctly? You may also want to vuse the VI analyizer to see how long things are taking to run. I would leave the producer consumer loop in the traditional set up and change the FPS by controlling the wait timer, after benchmarking your code this should be done the same way as you have it for the timed loop
Sam S
Applications Engineer
National Instruments

Share cluster data between 2 timed loops

What is the best and safest way of sharing cluster data between 2 timed loops running. I could use locals, but that is risky, would shared variables work better? All I need to do is modify a couple of datatypes in a cluster that both threads use.
Thanks...

You could go the LVOOP route and create a singleton object. The object can be passed to parallel tasks an dsince it is singleton they will all share the same value. Ue of a DVR inside the object would allow you to have a single copy of the data. Your class would also give you the necessary accessors for reading/writing data.
Mark Yedinak
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What is the best/most effective way to dynamically build a timed loop in LabView?

I am relatively new to labview (not to code in general) and am looking for the "LabVIEW" way to dynamically build a timed loop. This is what I am trying to accomplish:
I have several heaters controlled through labview using Labview's PID toolkit. This works great. I have no issues with DAQ in general. However, throughout an experiment, I want to change the set point of each heater. I could set this up fairly easily using either a timed loop or the wait vi if I knew exactly how many different set points there would be.
If possible, I would like to be able to read in a config file that includes the different times and set points for all heaters and dynamically create a loop that can handle this. I have tried using the Elapsed Time vi with an array of time targets; however that didn't seem to work.
Has anyone been able to do this? Does anyone know where I could learn about using LabView in this manner? All help is appreciated.

DHagan wrote:
I am relatively new to labview (not to code in general) and am looking for the "LabVIEW" way to dynamically build a timed loop. This is what I am trying to accomplish: I have several heaters controlled through labview using Labview's PID toolkit. This works great. I have no issues with DAQ in general. However, throughout an experiment, I want to change the set point of each heater. I could set this up fairly easily using either a timed loop or the wait vi if I knew exactly how many different set points there would be. If possible, I would like to be able to read in a config file that includes the different times and set points for all heaters and dynamically create a loop that can handle this. I have tried using the Elapsed Time vi with an array of time targets; however that didn't seem to work. Has anyone been able to do this? Does anyone know where I could learn about using LabView in this manner? All help is appreciated.
Write a tab-separated spreadsheet file makes it easy to use the write/read from spreadsheet files. Assuming you have a 2D-array of your times and set points it's just a question of setting up a for-loop going through the array row-by-row and extract the elements (expanded index array) to set your points and wait time.
/Y
LabVIEW 8.2 - 2014
"Only dead fish swim downstream" - "My life for Kudos!" - "Dumb people repeat old mistakes - smart ones create new ones."
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Timed Loop timing source - Control Loop From Task is too slow

I'm trying to make a Timed Loop run at a period of 2 ms, with an analog input task running at 50 kHz as timing source. The input analog signal is scaled and fed into a synchronised analog output task on the same multifunction DAQ board. Using the built-in 1 kHz or 1 MHz clock as timing source for the Timed Loop works great, except for a slight time lag between the loop and my AI/AO tasks which over time becomes unacceptable because my task will be running for up to an hour. However, when I use the DAQmx Create Timing Source: Control Loop From Task vi to create a timing source, everything slows down and the fastest loop time I can get is around 20 ms. Any suggestions to get around this would be highly appreciated!
System: LabVIEW RT 8.0 with DAQmx 8.0 running on an NI PXI-8186; NI PXI-6251 used for analog input.

You're welcome!
You can build an array, and if your data is not hugh (100's of MB) this may be the easiest solution. However, we aways suggest implementing the Producer/Consumer Architecture. Keep the PID in the Producer loop, but move the File IO to the Consumer. Also, it appears that your instrument uses some form of serial communication, so that could cause lags in your system....
What is your application about in general, what performance are you hoping for, etc?
Joshua B.
National Instruments
NI Services
NI Support Resources
NI Training Resources

Unable to run Timed Loops

Bit of an odd one that had me scratching my head.
I have a development system consisting of a PC running a 7842R, acquiring analogue and digital data from the FPGA, loading it into a shared variable, and reading it out within a timed loop on the host as one parallel loop in a producer-consumer architecture.
All's well until one day last week when I noticed my host VI becoming unresponsive.
After a bit of digging, I find that the timed loop doesn't run at all. Replacing with a while loop with a wait at least allows me to show that the error is timed loop related, but it's not a viable long term option for me. Creating a new project and a new VI with a simple timed loop showed the same behaviour.
A restart of the system, and rerunning the same VIs, and no problems since.
So, questions:
1) Has anyone else seen this behaviour?
2) Any idea what causes it? A service crashing, for example?
3) Is there a way of recovering without a reboot? If it's a service crash, I'm hopeful.
The system will eventually form part of a production test environment, hence the query.
Edit - also, wiring error terminals of a timed loop is a good way of highlighting errors of course.
FWIW, LV2012 SP1 32bit, Win7 64bit, Core2 Duo, 4GB RAM, tassels from the handlebars etc.
CLD

The timed loop is used to read all elements from a DMA FIFO and load them into a buffer FGV, which spits out packets of N samples long once they've assembled within the FGV. Ordinarily, I'd do this with a timed while loop and be perfectly happy to do so. However, the elements are actually an interleaved array, meaning that I have to demux them in the correct order that they were loaded.
I use timed loops for a number of reasons: on my current Windows host, I've found that using a while loop has caused me more problems with respect to disordered packets, and that at least with using multiple timed loops (two, at most), I can assign priority to the acquire loop. Finally, it's also a development platform, and will be deployed onto an sbRIO once the electronics integration is finished in a week or two!
W.r.t. system resources, there's very little else running on that system, but that doesn't normally stop Windows
I recognise it's not ideal to run a software timed loop under Windows, but when you cannot run a blank project with Optimizing timed loop rate.vi from the shipped examples with nothing else running, it makes me curious to know why!
CLD

Memory leak in Real-Time caused by VISA Read and Timed Loop data nodes? Doesn't make sense.

Working with LV 8.2.1 real-time to develop a host of applications that monitor or emulate computers on RS-422 busses. The following screen shots were taken from an application that monitors a 200Hz transmission. After a few hours, the PXI station would crash with an awesome array of angry messages...most implying something about a loss of memory. After much hair pulling and passing of the buck, my associate was able to discover while watching the available memory on the controller that memory loss was occurring with every loop containing a VISA read and error propogation using the data nodes (see Memory Leak.jpg). He found that if he switched the error propogation to regular old-fashioned shift registers, then the available memory was rock-solid. (a la No Memory Leak.jpg)
Any ideas what could be causing this? Do you see any problems with the way we code these sorts of loops? We are always attempting to optimize the way we use memory on our time-critical applications and VISA reads and DAQmx Reads give us the most heartache as we are never able to preallocate memory for these VIs. Any tips?
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GDLS
Solved!
Go to Solution.
Attachments:
Memory Leak.JPG ‏136 KB
No Memory Leak.JPG ‏137 KB

Hi thisisnotadream,
This problem has been reported, and you seem to be exactly reproducing the conditions required to see this problem. This was reported to R&D (# 134314) for further investigation. There are multiple possible workarounds, one of which is the one that you have already found of wiring the error directly into the loop. Other situations that result in no memory leak are:
1. If the bytes at port property node is not there and a read just happens in every iteration and resulting timeouts are ignored.
2. If the case structure is gone and just blindly check the bytes at port and read every iteration.
3. If the Timed Loop is turned into a While loop.
Thanks for the feedback!
Regards,Stephen S.
National Instruments
Applications Engineering

CVS-1458RT - ISO I/P triggered timed loop

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