Boolean triggered timed loop

Good afternoon Labview board,
I'm building code that turns a mouse click into a 2sec boolean true (indicator). My requirements are that...
1. Once the 2sec passes the boolean switches back to false.
2. The user is unable to re-trigger the process until it returns false.
I have attached a LabView v8.6 VI. It works, but very poorly. It often misses the mouse click, and has an unwanted latency.
Any help improving or redesigning it would greatly appreciated!
Thanks,
super-neuron
Attachments:
Untitled 2.vi ‏21 KB

Hi Super,
Have modified a VI i used a while back to do something similar:
I have made this into a subvi so you can use it as shown below:
I have attached both the subvi and example vi below in 8.6.
Hope it is what you need.
Regards,
Lucither
"Everything should be made as simple as possible but no simpler"
Attachments:
Timed True Latch.vi ‏38 KB
Timed True Latch Example.vi ‏7 KB

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Missed iterations of TTL triggered timed loop

Hello everyone,
I have a camera control VI that waits for TTL information from the camera shutter and uses it as a timing source for a timed loop. In this timed loop the camera is readout and analyzed. The program should react as soon a possible to a new image and therefore I set the timed loop to 'Discard missed items' so that it doesnt try to catch up (the events im trying to detect are quite rare and last several frames).
The problem is this: When I set the camera for a certain numebr of frames (for example 10.000 frames) sometimes due to the discarded frames the loop iteration number never reaches the expected last frame number and doesnt exit (it stays at 9.998 for instance). I noticed I can prevent this by deselecting 'maintain original phase' . However it is unclear to me what exactly happens with these settings in a TTL triggered situation like this.
Is it the case that the loop skips the new data but starts the next loop at the correct iteration number (+1)? Or is something else happening?
Im thankfull for any help!
Solved!
Go to Solution.

Dear j.win,
If you deselect "Maintain Original Phase", actually you will never discard any iteration, whatever the value of "Discard missed items". Instead, the loop will try to catch up with the late iterations.
Using an external timing source (your TTL for example) instead of an internal timing source does not change anything. You can use the "Period" (dt) input of the Timed Loop to specify when the loop is supposed to iterate (the unit is the "ticks" in the case of an external timing source). A value of "1" means that the Loop try to iterate at every ticks of the external timing source. If for some reason one iteration lasts longer than that, you will have a "late iteration". Also with a value of "1", it is not possible to modify the "phase", then the "Maintain Original Phase" parameter will just defined wether or not you skip the iteration. If "Maintain Original Phase" is false, the loop will execute immediatly after a late iteration to still execute it, but a bit latter. If the "Maintain Original Phase" is true, the loop will execute immediatly after a late iteraion if the "Discard missed item" is false otherwise the loop will skip the iteration.
Is it clearer now?
Regards,
Cédric | NI Belgium

CVS-1458RT - ISO I/P triggered timed loop

Hi everyone,
I am developing a real-time machine vision application on a CVS-1458 RT.
What I am aiming is a timed loop that is triggered via external clock (in my case a photoelectric sensor connected to an ISO input). All examples I can find are related to DAQmx devices, nothing related to visionRIO.
Question 1: Is this the best way to construct the acquisition loop? I want it to be condition based as to free-up the CPU from continous polling. If not, wht is the best way ?
Question 2: If the above method is OK, how can I setup the input node of my timed loop in a way to implement this ?
Thank you,
Omar

Hi Omar,
I was able to find some Vision-RIO examples in the Example Finder of LabVIEW. If you open LabVIEW and navigate to Help>> Find Examples.
In the Example Finder in the Browse tab navigate to Hardware Input and Output>> Vision Acquisition>> Vision-RIO.

LabVIEW RT, Timed loop, finished late, Call by reference

I have a timed loop triggered by the sample clock of a DAQ-Card. The sample Clock is 8 kHz and the loop will run with dt = 4. Normally the loop is running without finished late[i-1]. But from time to time it happens that the loop is running extremly longer which means instead of 0.5 millisec it needs 4 - 5 millisec. It seems this doesn't never occur while accessing DAQmx.
The application uses plugin technologies and some of the VIs in the timed loop are preloaded and called by Call by Reference.
Does those VIs inherit the priority, execution system and CPU of the timed loop?
The application is running on LV RT 2009 on a Dual core PXI-Controller. The timed loop is bound to CPU 1. There is no difference runinng the application from the development environment or as a startup application.
For the measuring test I modified the application in a way that I don't have:
disk access for storing the result file
TCP/IP communication
Controls on the front panel of the top level VI
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

To keep you informed:
I stripped the application and have left only the measurement storing module and the timed loop. The loop was using the microsecond timer running each 500 µsec. Additional all Non-Real-Time modules were loaded and only one module creates a XML string and sends it to the communication layer which will drop it because no TCP/IP port is open. The creation of the XML string is done each 300 ms.
In this case I don't have any finished late iterations
Next I added the DAQ Module. Now I get finished late again but with a lesser frequency as original.
I removed all unnesseccary tasks from the DAQ moulde leaving one task for a PXI-4204 for using as the clock source for the timed loop. No I get finished late seldom.
I removed the module which will send the XML string and I don't get finished late.
Next I was adding code to see memory allocation. I can when memory allocation is changing but it is not related to the finished late iterations.
Next time I have the chance to do more tests I will see which DAQ task triggers the finished late iterations. I have one AI task on a PXI-4204, 4 Counter tasks on a PXI-6602, 1 DI task on a PXI-6514, 1 DO task on a PXI-6514, 1 DI task on a PXI-6259, 1 DO task on a PXI-6259, 1 AO task on a PXI-6259 and 1 AO task on a PXI-6711.
The AI task on the PXI-4204 is running in Continous Sampling (Single Point HW Timed is not supported), all other tasks exept the DI and DO are Single Point HW Timed.
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

Timed loop inside a flat sequence not terminating

Inside a while loop there is an event structure. Inside that there is a flat sequence. On one of the frames there is a timed loop that quits after so many iterations. The timed loop finishes but the flat sequence doesn't execute the next sequence. What am I not doing right?

First, you have too many local variables. This could be leading to race conditions.
I think you have a couple problems in the use of event structures. It is a bad idea to put any long running code inside an event case. It will prevent the Event Structure from handling any other events in the mean time. You have several timed loops running that in that one sequence frame.
But the bigger problem is the next sequence frame. You have a while loop that only ends once all the queues are empty. Can you guarantee that all the queues get emptied?
You have laid out the code very neatly, but you have used a lot of odd things in there. (Number to boolean array, to cluster, to unbundle the cluster to individual indicators.) Why not just go from Boolean array to and index array function. No need for the intermediate cluster conversion. Why not set up the indicators as an indicator array and just write to them directly.
The code is so much intertwined between when queues are created, filled, emptied, destroyed, events happen... And this is all multiplied by at least 4 times for each camera. And there are 4 major event structures going on. This is a very ambitious project for an inexperience LabVIEW user. You need to step back, get one thing working right, and design so that you can scale the architecture upward. Many of the structures you have essentially duplicated and belong in subVI's.

Timed loop with array dimension control

Hello,
I have imported an excel to an array and im trying to use a timed loop to run the values of the array on a timed interval. One of my problems is that the array is 2D and i cant use its length to stop the loop. I want to use witch value of the array in the loop in each iteration of the loop and i want the loop o stop when the counter equals the length of the array. Can someone help me plz here is the labview.

It is really unclear what your question is. Could you clarify?
If you are struggling with why you have a broken wire it is because you are sending an array to the stop of the loop. When you use the array size function on a 2D array it returns a 1D array with the size of each dimension. When you then use the greater than function it returns a 1D array of Booleans. It compares each element of the array size to the current count of the iteration terminal.
To use this to stop your loop you need to reduce it to a single element some way before you send it to the stop control of the loop. You could apply an "and" or "or" function to the out put of the greater than or pull out a single index out of the single greater than array.
In the image logical AND, logical OR, or element could be used to stop the loop. You just need to choose one that gives you the behavior you need.
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How can I count the number of times a timed loop finished late?

I am getting occasional timing errors in a timed loop under windows XP and would like to count the number of errors, but I can't find a simple software counter vi

The timed loop has a terminal (boolean) to indicate if the previous iteration finished late. Just increment an integer shift register if this happens.
The attached shows a very simple demo (LabVIEW 7.1).
LabVIEW Champion . Do more with less code and in less time .
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LateCounter.vi ‏76 KB

Two timed loops separate but connected

Hi,
I have a simple Data Acquisition setup where I read 32 voltages, and write them to file. I want my front panel to update the displayed voltages every 2 seconds, but only want the same values to be written to file every 5 minutes.
I've tried nesting one timed loop in another, but the displayed values update at the same time interval as the write to file (Write-to-file loop nested in main timed loop).
I've also tried creating one timed loop for the display (2 second interval) and a separate timed loop for the write to file (5 min interval). However, while the display updates, the write to file does not work.
I just want two timers working simultaneously, but one gets data from the other after 5 minutes.
Sorry if this is a repeat post, but I couldn't find answers elsewhere.
Thanks in advance,
Walter Kaminski

Hello:
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I attached a small example.
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Attachments:
Time Intervals.vi ‏64 KB
time invervals.JPG ‏38 KB

Timed loop and CPU usage

Platform is WIN_XP Pro and machine is a P4 at 2.5Ghz with 512 Mb ram.
LV7.1 + PCI 6229
I am using 50ms Timed loop for running a state machine inside it
and also a whole lot of other things like reading / writing
DAQMx functions; file I/O functions and such. As the
project involves a main and sub-panlel set up local variables
could not be elimnated fully and there should be something like 150 of
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Problem :
Once started the "Finished late" indication is off and
the actual timing alternates between 49 to 52 ms. The CPU
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Obviously the machine control timing now gets affected and things slow
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I am at a loss to understand what is happening ? WIll
breaking down the single Timed Loop to multiple ones help ? WIll
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thanks
Raghunathan
Raghunathan
LV2012 to Automate Hydraulic Test rigs.

Hello,
It sounds like an interesting problem. It would be worth some experimentation to figure out what's going wrong - attempting to decouple major "pieces" of the code would be helpful. For example, you could try breaking your code into multiple loops if that makes sense in your architecture, but perhaps you could even eliminate all but one of the loops to begin with, and see if you can correlate the problem to the code in just one of your loops.
Another concern is that you mention using many local variables. Variable read operations cause new buffer allocations, so if you're passing arrays around that way, you could be hitting a problem of forcing your machine to perform many allocations and deallocations of memory. As arrays grow, this can be a bigger and bigger problem. You can use other techniques for passing data around your block diagram, such as dataflow if possible (just simple wires), or queues where dataflow can't dicatate program flow completely.
Hopefully looking into your code with the above considerations will lead you in the right direction. In your case, removing code so that you can identify which elements are causing the problem should help significantly.
Best Regards,
JLS
Best,
JLS
Sixclear

Logc 7.1 drops when triggering MIDI loops?

I have an Akai sampler, and when i trigger loops within logic 7 via midi, at the end of every bar the Logic stops the loop short of the bar?
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This is fine on my G5 OSX with 4Gb , triggering the loops on ableton or Protools, only with Logic?!
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update:
Apple technician told me the way Logic uses cores changes depending on it's application.... ugh

Questions about parallel and series sturcture in SCTL (single clock timed loop) in FPGA VI

I am using LV 8.2.
I have wriiten a FPGA VI, in this VI, there are 3 filters inside the SCTL (single clock timed loop) (I use the shift register to be the effect of unit delay). Would I save the resources of the FPGA used (such as slices and LUT) in the compliation report if I use 3 SCTL ( 1 SCTL contain 1 filter) and cascade them in series?
Thank you!

Sorry, I am afraid that you have misunderstood my meaning.
Here is the method you suggested before:
I mean I use the shift registers attached in the while loop, not in the SCTL. The number of shift registers used will not be decreased when we increase the number of SCTL in the second plate of the flat sequence structure. Totally , there are 6 pairs shift registers for 3 filters (1 filter needs 2 pairs). I mean I put the calculation parts, such as b0*x[n]+b1*x[n-1]+b2*x[n-2] inside the SCTL ( the operations of multiplication and add). Instead of putting 3 filters numeric operation part in one SCTL. will we reduce the resources used if we use 1 SCTL to do the operation parts of 1 filter? As the code inside each SCTL will be reduced.
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Can I run a fast timed loop?

It appears that a timed loop cannot run faster than 100 hz. In other words, the "period" input for a timed loop cannot be less than 10. Is this true? I am using the Elapsed Time VI to measure time increments. The time increments output from this VI are at least 0.01 secs regardless of how fast I attempt to run the time loop. Perhaps the limitation lies in the Elapsed Time VI, not in the Timed Loop. Should I try a different approach to measuring the delta time between iterations of a time loop? TIA.
-jlivermore

Here's the simple way to measure loop timing:
Actually, what else is running in your loop (e.g. property nodes, DAQ, etc.)? Can you show us your code? What is your LabVIEW version?
Message Edited by altenbach on 09-29-2008 11:22 AM
LabVIEW Champion . Do more with less code and in less time .
Attachments:
MeasureLoopTiming.PNG ‏7 KB

Using timer/counter with PCI-6221/USB-6210 to control timed-loop VI

Dear all,
I need to ask about two devices and one of their functionalities, PCI-6221 and USB-6210. For our NI-based system, we need to control some timings in a Timed-Loop vi, for that currently we are using PCI-6221 and we give external TTL signal (at 1 kHz) to it,
recenntly we need to make some changes and for that we found USB 6210 DAQ to be more suitable, but we need to clear ourselves on some specific things.
Can the counter/timers functions available in the either PCI 6221 or USB 6210 can be used to control the Timed-loop VI by giving external clock or by using their own internal clock source?
Although we are using external clock with the PCI 6221 but we want to know about the usage of their internal clock, also are controlling timed-loop also possible for USB-6210
Also... What if we use the RTOS, are they still able to control the timed-loop VI without giving any 'EXTERNAL CLOCK' and using the internal clock sources of the DAQs
Waiting for reply,
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RaJaf
Solved!
Go to Solution.

Ben,
I having read previous email which I send earlier with general overview, we discussed in more detail within our team and I am giviing the specific answers.
Please check in RED the most recent answers. Blue are the questions/suggestions by your side.
1.    Using Internal hardware clock of PCI-6221 would enable us get rid of external clock, but how to divert the internal hardware clock to the current settings. Any idea (can you provide us with some reference manul for otherwise). I mean is there some flag-bit etc. or VI
2.       Is it also meant that with the installation of RTOS the timed-loop can directly get the timing source from the internal hardware clock PCI-6221? --- How???
3.       In order to make desktop to work as RT system, what is the hardware (motherboard, processor, etc..) requirement? What are the LabVIEW modules (specific name) that needed to be installed? Our platform is LabVIEW 8.6. (Currently we have windows-7 with i7 core processor)
What kind of application are you intending for this system? ---- high-speed laser scanning system.
Are you most concerned about accuracy, speed, or responsiveness? To control the laser mirror scanner to move at 1 kHz or 2 kHz speed. On the other hands, using PCI-5105 (128 MB memory) as a DAQ for real-time/on-the-fly data processing.
Bests,
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Timed Loop in Producer/Consumer Loop

Hello!
I have a producer/consumer loop LabVIEW program setup to allow me to properly capture images that are quite large (8MP) at approximately 14 frames per second (FPS). The program works great when the consumer loop is a 'while loop' (records at 14fps no problem), but I wanted to make it into a timed loop, so that I may vary the FPS as required. An oddity arises when I do this. Anywhere below 12fps, the loop works fine and the data is recorded properly. However, when I bump it up to 13fps, the consumer calculated FPS goes haywire and starts jumping between ~9 and ~13fps (data processing gets bogged?). When I set the required FPS to 14, the loop executes at a steady 7FPS maximum. Is there something I can do to rectify this situation?
I have attached my .VI
Thanks in advance!
Solved!
Go to Solution.
Attachments:
ProcessSplitJPG-FPS.vi ‏100 KB

Palanski,
Are you using LabVIEW Real-Time? Timed loops in a windows OS don't really increase determinism more than a while loop with a wait until next multiple timer. Before you changed the producer consumer loop to include a while loop was the programming running correctly? You may also want to vuse the VI analyizer to see how long things are taking to run. I would leave the producer consumer loop in the traditional set up and change the FPS by controlling the wait timer, after benchmarking your code this should be done the same way as you have it for the timed loop
Sam S
Applications Engineer
National Instruments

Share cluster data between 2 timed loops

What is the best and safest way of sharing cluster data between 2 timed loops running. I could use locals, but that is risky, would shared variables work better? All I need to do is modify a couple of datatypes in a cluster that both threads use.
Thanks...

You could go the LVOOP route and create a singleton object. The object can be passed to parallel tasks an dsince it is singleton they will all share the same value. Ue of a DVR inside the object would allow you to have a single copy of the data. Your class would also give you the necessary accessors for reading/writing data.
Mark Yedinak
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Boolean triggered timed loop

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