Data Capture on Host VI without Massive FIFO?!?

Question

Hi guys,
First post on the boards and about two weeks into LV Realtime/FPGA so be gentle!
I'm capturing data from a system using a CRio 9082 and NI9215 A/D converter. The FPGA vi runs a timed loop (10 us or 100kS/s) which pulls in data and sends it to a Target-to-Host DMA FIFO (4096 long, single precision). Since I want to synchronise data acquisition to a TTL output, the FPGA also sends out a True/False value through a DIO port (NI9402). So, for example, if I want a 100 Hz TTL pulse and the loop time is 10 us, then a full TTL cycle will last 1000 loops with the half cycle lasting 500 loops. Both the position in the TTL cycle (0-1000) and the data acquired at that position in the cycle are interleaved in the FIFO. I've attached an image of the VI.
The Host vi simply reads the values from the FIFO, decimates the interleaved output, and stores the data in an array for subsequent processing. I've also attached an image of the Host vi. The problem is that the data acquisition time could be as high as 10 seconds, which would mean the host-side FIFO would be 2 million elements long!
SO, my question is how do I modify the host vi so that instead of waiting for the host-side FIFO to be filled, its size can be reduced and yet not lose data points in the filling of the array? You might rightly ask why I've done things that way but I found that filling up a massive FIFO ensures that I don't lose the continuous TTL position data, but then I figured it was grossly inefficient and some sage advice is necessary! 
Thanks!!  
Solved!
Go to Solution.
Attachments:
FPGA.png ‏31 KB
Host.png ‏20 KB

Answer 1

No problem.
Ordering issues in FIFOs have been a PITA for me for a while. Experimenting with different techniques suggests the following:
- Never let your FIFO fill up, otherwise you're just throwing data away. Make sure you sample often enough (and more importantly, remove enough samples) to avoid this.
- On this note, only fill up your FIFO when you choose to. You can use a sequence frame before the acquisition in the RT loop, dump in a While loop and wire a control to the stop terminal. You can then switch this to true in the host application when you're ready to receive data.
- Timed loops (or while loops with timers) probably won't execute in a consistent manner on a Windows system. If you're hoping to acquire 10000 samples consisting of two channels every 100 ms, the loop might execute every 101 ms if you're unlucky. This means there may be more data in your FIFO, and you may not necessarily have an integer multiple of the number of channels. So if you have two channels, and there are only five samples in the FIFO when you come to read, the next sample into the FIFO (and thus the next sample out!) will no longer be in the same order as the previous packet.
- How do you get round this? Well, you can buffer your data in: run the timed loop more quickly, read all the elements available in the FIFO and concatenate the resulting array with the previous iteration via a shift register. Keep doing this until the concatenated array reaches the requisite number of samples (e.g. your 10000 samples earlier) and then offload the results upstream, reinitialising the array to which you concatenate elements. Kudos to my colleague, -K-, for suggesting this to me.
- Remember to stop the target from filling the FIFO when you have all the data you want, and to empty the FIFO and dispose of any additional data that may have been lobbed in there.
CLD