Data Validation in XML Spreadsheet 2003

Hi,
try this:
1) create new Excel worksheet
2) select A1:A10
3) set Data Validation to List, on Sheet2!A1:A10
4) save the file as XML Worksheet 2003
5) reopen the file
6) data validation does not work anymore
is this a bug?

Hi
You don't say what version of Excel you are using. However I can confirm that the feature does fail when following your method in 2010.
The file type you are using does not support "Data Consolidation References" (see help in propmt when saving file).  This includes linking between sheets.  You'll notice your data validation source becomes =sheet2!#REF.
If the list was on the same sheet then the validation would work.
Hope this helps
G North MCT

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    import oracle.iam.request.vo.RequestData;
    +public class TestRequestValidator implements RequestDataValidator {+
    +public TestRequestValidator() {+
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    System.out.println("************************************************");
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  • Vivado 2013.4 ERROR: [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order

    Hello,
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    [HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen_demo.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen_demo.vhd":1]
    Analysis Results[IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
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    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    [HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen.vhd":1]
    [IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    set_property target_language Verilog [current_project]
    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    sources_1[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    [HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen_demo.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen_demo.vhd":1]
    [IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    [IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    update_compile_order -fileset sim_1
    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    [HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/fsm.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/fsm.vhd":1]
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/fsm.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/fsm.vhd":1]
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    [HDL 9-1654] Analyzing Verilog file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sim/testbench.v" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sim/testbench.v":1]
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/debounce.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/debounce.vhd":1]
    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2013.4/data/ip'.
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    [IP_Flow 19-1704] No user IP repositories specified
    [IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    Vivado Commands[Project 1-11] Changing the constrs_type of fileset 'constrs_1' to 'XDC'.
    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    sim_1[IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [HDL 9-1654] Analyzing Verilog file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sim/testbench.v" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sim/testbench.v":1]
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    [IP_Flow 19-234] Refreshing IP repositories
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    [IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    [IP_Flow 19-395] Problem validating against XML schema: Invalid value format for this type spirit:order
    [IP_Flow 19-193] Failed to save BOM file '/home/jmassol/.Xil/Vivado-2683-ubuntu/coregen/dds_compiler_0/dds_compiler_0.xml'.
    [IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    [HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/debounce.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/debounce.vhd":1]
    [IP_Flow 19-3378] Failed to create IP instance 'dds_compiler_0'. Error saving IP file.
    [IP_Flow 19-194] Failed to save IP instance 'dds_compiler_0'.
    [HDL 9-1061] Parsing VHDL file "/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen.vhd" into library work ["/home/jmassol/Desktop/Vivado/vivado_debug/ug937/project_xsim/project_xsim.srcs/sources_1/imports/ug937/sources/sinegen.vhd":1]
    set_property constrs_type XDC [current_fileset -constrset]
     

    We had the same problem when switching to Ubuntu 14.04, and there actually is a solution for it: make sure your locales are set to English.
    $> env | grep LC_*
    should only show english (or C) locales, all others are known to cause parsing errors in some numbers, usually caused by wrong string-to-float conversions (e.g. 18,29 in german is 18.29 in english). You can change the locales in the file /etc/default/localesThis is not the first time we had problems with the locale settings, Xilinx does not seem to test their software with anything else than en_US, causing obscure bugs like this one.
    HTH
    Philipp

  • PO Confirmation with Delivery Date Validation Check

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