DCache Misses and Line Replacements in disabled mode

Question

The Dcache is write through which i believe operate in following modes
1.What are the situations that need the Dcache to operate in Disabled mode?
2.In the disabled mode all the data is fetched from L2 regardless of a cache hit or miss?
3.In normal mode does only TSO compliant stores that miss the data cache bring the line back to Dcache or missed stores dont allocate a line in Dcache?
4.So in RMO stores misses the line is never brought to cache from L2?

Answer 1

The Dcache is write-through, and stores are non-allocating.
1. By "disabled mode", I assume you mean D-cache disabled. D-cache is disabled when the processor is reset. Part of the reset process is to zero out all the valid bits for all ways and indexes before the D-cache can be enabled. The system would only run with D-cache disabled if there were some defect that prevented the D-cache from operating correctly.
2. In disabled mode, all loads go to the miss buffer, which forwards them to L2. When data comes back, D-cache is not updated. Stores are handled pretty much the same, because they are non-allocating, and write-through. L2 will never indicate a store hit in D-cache, so the D-cache will never be updated by the store.
3. As discussed before, stores that miss the D-cache are non allocating. Stores that hit the D-cache are updated only after L2 responds with store-ack, indicating D-cache hit.
4. RMO stores (RMO stands for Relaxed Memory Ordering). With RMO stores, there is no requirement that loads occurring after a store should see the stored value. It's a don't care. RMO stores are de-queued from the store queue immediately after they are sent to L2. RMO stores never update the D-cache. If L2 returns a store ack indicating D-cache hit, the line is invalidated. What does this mean? If a load follows an RMO store to the same address, it may see either the old value or the new stored value, depending on the timing. If the load occurs before the store buffer sends the store to L2, it may hit in the store buffer (It's an implementation detail. I don't know whether loads are allowed to hit on RMO stores or not). After the RMO store is sent to L2, it is de-allocated from the store queue. the load might hit in D-cache, which would supply the old value of that location. After the store ack is received, the D-cache line is invalidated, so a load request must be sent to L2, which will supply the new value.
formalGuy