DMA question

I've read Writing Device Drivers, but I've still got a few holes in my understanding of the dma routines.
I'm developing a driver for a PCI device that requires a very high sustained data rate, so I'm looking for every way possible to improve throughput. The device will be on a dedicated machine, so taking resources away from other processes is not an issue. We will have a pool of large (~64 MB) buffers in user space and a user process will notify the driver when the contents of a buffer need to be transferred to the device. The device will perform DMA to transfer the buffer contents to the card.
I would like to be able to allocate a few DMA handles (using ddi_dma_alloc_handle) in the attach entry point and use these handles to transfer the large buffers. Will I be able to allocate handles for such large DMA objects?
When initiating the transfer, I would get an unused pre-allocated DMA handle (via ddi_dma_addr_handle ?) and program the DMA engine on the device. Does this copy the contents of the buffer from user space to kernel space? If it does, is there a way to avoid this copy?
Thanks in advance for any help you can provide.

Oops. Just caught I typo in my previous message. I was planning on using ddi_dma_addr_bind_handle to get an unused pre-allocated DMA handle. Or would I want to use ddi_dma_buf_bind_handle? When is each one appropriate?

Similar Messages

Labview 8.0 FPGA DMA question

I am developing a control system which needs to access a big mass of
variable data (32 Mbyte) that i can put into the host computer RAM. In
labview tutorial and also on other web resources it is well described
how the DMA FIFO can be used to "write to" host PC memory (RAM) but
nothing about "reading from" the PC RAM. Is it possible? And which is
the control to be used? Do I need some lower level coding?
Thanx
Davide

Hi Davide,
As of right now, the DMA transfers are one-way only (FPGA to host).
Best regards,
David H.
Systems Engineer
National Instruments

Host to Target DMA question

Hello Guys,
I have a problem regarding DMA Access from Host to Target. I access DMA at an interval of 1.7uS I get 12 U32 data from DMA every 1.7uS, problem is, I can see that DMA can take more time than the normal. Is there a more efficient way to get 12 U32 data at a time?
Thanks,

Hello Jeremy
I am using NI 7833R FPGA module. what I did was to place read DMAs in a sequence structure (1 in each frame so that makes 12 frames). then inside each frame, I placed an output port which I set to True then false then true agan while passing through the sequence structure.
When I run the program, I can see that it takes around 125nS for each DMA access, But there are times that it takes more time to complete 1 access which takes more than 125nS.Most of the time, The 12 U32 data takes 1.5uS to complete. But due to the unknown reason, it sometimes takes more time to access DMA.
Thanks

/ usage questions...

Hello.
I have 2 questions:
1. I have noticed that my / partition's used space increased by ~10M from the last time I've checked it, from 111M to 121M. What could be the cause of that? (see the info below...)
2. The output of df and du is not what I am expecting it to be. I.e. there are differences between the disk usage reported by these 2 commands on the / partition. What could be the cause of this? (see the info below...)
Any reply or any RTFM re-dirrectioning is appreciated.
TIA
Info:
[root@guns /]# df -h
Filesystem Size Used Avail Use% Mounted on
/dev/ide/host0/bus0/target0/lun0/part5
189M 121M 68M 65% /
none 235M 0 235M 0% /dev/shm
tmpfs 235M 4.0K 235M 1% /tmp
/dev/ide/host0/bus0/target0/lun0/part2
31M 5.2M 24M 18% /boot
/dev/ide/host0/bus0/target0/lun0/part6
2.4G 713M 1.7G 30% /usr
/dev/ide/host0/bus0/target0/lun0/part7
1.9G 374M 1.5G 20% /var
/dev/ide/host0/bus0/target0/lun0/part8
57G 35G 23G 62% /home
/dev/ide/host0/bus0/target0/lun0/part9
957M 486M 472M 51% /opt
[root@guns /]# ls
bin boot dev etc home lib mnt opt proc root sbin sys tmp udev usr var
[root@guns /]# du -sh bin/ dev/ etc/ lib/ mnt/ proc/ root/ sbin/ sys/ tmp/ udev/
2.8M bin/
0 dev/
5.5M etc/
64M lib/
0 mnt/
481M proc/
12M root/
5.2M sbin/
du: cannot access `sys/bus/pci/drivers/Intel(R) 830M/845G/852GM/855GM/865G Framebuffer Driver': No such file or directory
0 sys/
4.0K tmp/
0 udev/
Here's my dmesg output in case it helps...
Linux version 2.6.11.7-ARCH (root@earth) (gcc version 3.4.3) #1 SMP Sat Apr 9 13:37:54 PDT 2005
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000001dffc000 (usable)
BIOS-e820: 000000001dffc000 - 000000001dfff000 (ACPI data)
BIOS-e820: 000000001dfff000 - 000000001e000000 (ACPI NVS)
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
0MB HIGHMEM available.
479MB LOWMEM available.
On node 0 totalpages: 122876
DMA zone: 4096 pages, LIFO batch:1
Normal zone: 118780 pages, LIFO batch:16
HighMem zone: 0 pages, LIFO batch:1
DMI 2.3 present.
ACPI: RSDP (v000 ASUS ) @ 0x000f6b10
ACPI: RSDT (v001 ASUS A7VI-VM 0x30303031 MSFT 0x31313031) @ 0x1dffc000
ACPI: FADT (v001 ASUS A7VI-VM 0x30303031 MSFT 0x31313031) @ 0x1dffc080
ACPI: BOOT (v001 ASUS A7VI-VM 0x30303031 MSFT 0x31313031) @ 0x1dffc040
ACPI: DSDT (v001 ASUS A7VI-VM 0x00001000 MSFT 0x0100000b) @ 0x00000000
ACPI: PM-Timer IO Port: 0xe408
Allocating PCI resources starting at 1e000000 (gap: 1e000000:e1ff0000)
Built 1 zonelists
Kernel command line: root=/dev/hda5 vga=773 ro
Local APIC disabled by BIOS -- you can enable it with "lapic"
mapped APIC to ffffd000 (013e3000)
Initializing CPU#0
PID hash table entries: 2048 (order: 11, 32768 bytes)
Detected 807.525 MHz processor.
Using pmtmr for high-res timesource
Console: colour dummy device 80x25
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 480548k/491504k available (4086k kernel code, 10360k reserved, 1236k data, 288k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay loop... 1597.44 BogoMIPS (lpj=798720)
Security Framework v1.0.0 initialized
Capability LSM initialized
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
CPU: After generic identify, caps: 0183f9ff c1c7f9ff 00000000 00000000 00000000 00000000 00000000
CPU: After vendor identify, caps: 0183f9ff c1c7f9ff 00000000 00000000 00000000 00000000 00000000
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 64K (64 bytes/line)
CPU: After all inits, caps: 0183f9ff c1c7f9ff 00000000 00000020 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
Enabling fast FPU save and restore... done.
Checking 'hlt' instruction... OK.
ACPI: setting ELCR to 0200 (from 0e00)
CPU0: AMD Duron(tm) Processor stepping 01
per-CPU timeslice cutoff: 182.83 usecs.
task migration cache decay timeout: 1 msecs.
SMP motherboard not detected.
Local APIC not detected. Using dummy APIC emulation.
Brought up 1 CPUs
CPU0 attaching sched-domain:
domain 0: span 1
groups: 1
domain 1: span 1
groups: 1
NET: Registered protocol family 16
PCI: PCI BIOS revision 2.10 entry at 0xf10c0, last bus=1
PCI: Using configuration type 1
mtrr: v2.0 (20020519)
ACPI: Subsystem revision 20050228
ACPI: Interpreter enabled
ACPI: Using PIC for interrupt routing
ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11 12 14 15)
ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 *10 11 12 14 15)
ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 *9 10 11 12 14 15)
ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *9 10 11 12 14 15)
ACPI: PCI Root Bridge [PCI0] (00:00)
PCI: Probing PCI hardware (bus 00)
PCI: Via IRQ fixup
ACPI: PCI Interrupt Routing Table [_SB_.PCI0._PRT]
ACPI: PCI Interrupt Routing Table [_SB_.PCI0.PCI1._PRT]
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
pnp: PnP ACPI: found 12 devices
PnPBIOS: Disabled by ACPI PNP
SCSI subsystem initialized
PCI: Using ACPI for IRQ routing
** PCI interrupts are no longer routed automatically. If this
** causes a device to stop working, it is probably because the
** driver failed to call pci_enable_device(). As a temporary
** workaround, the "pci=routeirq" argument restores the old
** behavior. If this argument makes the device work again,
** please email the output of "lspci" to [email protected]
** so I can fix the driver.
pnp: 00:02: ioport range 0xe400-0xe47f could not be reserved
pnp: 00:02: ioport range 0xe800-0xe80f has been reserved
pnp: 00:02: ioport range 0xe200-0xe27f has been reserved
Simple Boot Flag at 0x3a set to 0x1
apm: BIOS version 1.2 Flags 0x03 (Driver version 1.16ac)
apm: overridden by ACPI.
VFS: Disk quotas dquot_6.5.1
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
devfs: 2004-01-31 Richard Gooch ([email protected])
devfs: boot_options: 0x1
Installing knfsd (copyright (C) 1996 [email protected]).
SGI XFS with ACLs, security attributes, no debug enabled
SGI XFS Quota Management subsystem
Initializing Cryptographic API
Applying VIA southbridge workaround.
PCI: Disabling Via external APIC routing
vesafb: framebuffer at 0xf0000000, mapped to 0xde880000, using 1536k, total 32768k
vesafb: mode is 1024x768x8, linelength=1024, pages=41
vesafb: protected mode interface info at c000:7f88
vesafb: scrolling: redraw
vesafb: Pseudocolor: size=8:8:8:8, shift=0:0:0:0
Console: switching to colour frame buffer device 128x48
fb0: VESA VGA frame buffer device
ACPI: Power Button (FF) [PWRF]
ACPI: CPU0 (power states: C1[C1] C2[C2])
ACPI: Processor [CPU0] (supports 16 throttling states)
isapnp: Scanning for PnP cards...
isapnp: No Plug & Play device found
Linux agpgart interface v0.100 (c) Dave Jones
agpgart: Detected VIA Twister-K/KT133x/KM133 chipset
agpgart: Maximum main memory to use for agp memory: 409M
agpgart: AGP aperture is 64M @ 0xf8000000
[drm] Initialized drm 1.0.0 20040925
intelfb: Framebuffer driver for Intel(R) 830M/845G/852GM/855GM/865G chipsets
intelfb: Version 0.9.2
serio: i8042 AUX port at 0x60,0x64 irq 12
serio: i8042 KBD port at 0x60,0x64 irq 1
Serial: 8250/16550 driver $Revision: 1.90 $ 8 ports, IRQ sharing disabled
ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
Floppy drive(s): fd0 is 1.44M
FDC 0 is a post-1991 82077
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: loaded (max 8 devices)
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
spurious 8259A interrupt: IRQ7.
VP_IDE: IDE controller at PCI slot 0000:00:07.1
VP_IDE: chipset revision 6
VP_IDE: not 100% native mode: will probe irqs later
VP_IDE: VIA vt82c686b (rev 40) IDE UDMA100 controller on pci0000:00:07.1
ide0: BM-DMA at 0xd800-0xd807, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0xd808-0xd80f, BIOS settings: hdc:DMA, hdd:pio
Probing IDE interface ide0...
hda: Maxtor 6Y080L0, ATA DISK drive
hdb: HL-DT-ST GCE-8481B, ATAPI CD/DVD-ROM drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
Probing IDE interface ide1...
hdc: HL-DT-STDVD-ROM GDR8163B, ATAPI CD/DVD-ROM drive
ide1 at 0x170-0x177,0x376 on irq 15
Probing IDE interface ide2...
Probing IDE interface ide3...
Probing IDE interface ide4...
Probing IDE interface ide5...
hda: max request size: 128KiB
hda: 160086528 sectors (81964 MB) w/2048KiB Cache, CHS=65535/16/63, UDMA(33)
hda: cache flushes supported
/dev/ide/host0/bus0/target0/lun0: p1 p2 p3 p4 < p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 >
hdb: ATAPI 40X CD-ROM CD-R/RW drive, 2048kB Cache, UDMA(33)
Uniform CD-ROM driver Revision: 3.20
hdc: ATAPI 52X DVD-ROM drive, 256kB Cache, UDMA(33)
libata version 1.10 loaded.
mice: PS/2 mouse device common for all mice
input: AT Translated Set 2 keyboard on isa0060/serio0
psmouse.c: Failed to reset mouse on isa0060/serio1
input: PS/2 Generic Mouse on isa0060/serio1
psmouse.c: Failed to enable mouse on isa0060/serio1
md: linear personality registered as nr 1
md: raid0 personality registered as nr 2
md: raid1 personality registered as nr 3
md: raid10 personality registered as nr 9
md: raid5 personality registered as nr 4
raid5: measuring checksumming speed
8regs : 1080.000 MB/sec
8regs_prefetch: 1020.000 MB/sec
32regs : 812.000 MB/sec
32regs_prefetch: 764.000 MB/sec
pII_mmx : 2168.000 MB/sec
p5_mmx : 2904.000 MB/sec
raid5: using function: p5_mmx (2904.000 MB/sec)
raid6: int32x1 332 MB/s
raid6: int32x2 410 MB/s
raid6: int32x4 265 MB/s
raid6: int32x8 253 MB/s
raid6: mmxx1 675 MB/s
raid6: mmxx2 1136 MB/s
raid6: sse1x1 644 MB/s
raid6: sse1x2 1058 MB/s
raid6: using algorithm sse1x2 (1058 MB/s)
md: raid6 personality registered as nr 8
md: multipath personality registered as nr 7
md: md driver 0.90.1 MAX_MD_DEVS=256, MD_SB_DISKS=27
device-mapper: 4.4.0-ioctl (2005-01-12) initialised: [email protected]
NET: Registered protocol family 2
IP: routing cache hash table of 2048 buckets, 32Kbytes
TCP established hash table entries: 16384 (order: 6, 262144 bytes)
TCP bind hash table entries: 16384 (order: 5, 196608 bytes)
TCP: Hash tables configured (established 16384 bind 16384)
NET: Registered protocol family 1
NET: Registered protocol family 10
IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
ACPI wakeup devices:
PCI0 PCI1 UAR1 UAR2 USB0 USB1
ACPI: (supports S0 S1 S4 S5)
devfs_mk_dev: could not append to parent for md/0
md: Autodetecting RAID arrays.
md: autorun ...
md: ... autorun DONE.
ReiserFS: hda5: found reiserfs format "3.6" with standard journal
ReiserFS: hda5: using ordered data mode
ReiserFS: hda5: journal params: device hda5, size 8192, journal first block 18, max trans len 1024, max batch 900, max commit age 30, max t
rans age 30
ReiserFS: hda5: checking transaction log (hda5)
ReiserFS: hda5: Using r5 hash to sort names
VFS: Mounted root (reiserfs filesystem) readonly.
Mounted devfs on /dev
Freeing unused kernel memory: 288k freed
Adding 96380k swap on /dev/discs/disc0/part3. Priority:-1 extents:1
Adding 96348k swap on /dev/discs/disc0/part10. Priority:-2 extents:1
kjournald starting. Commit interval 5 seconds
EXT3 FS on hda2, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
ReiserFS: hda6: found reiserfs format "3.6" with standard journal
ReiserFS: hda6: using ordered data mode
ReiserFS: hda6: journal params: device hda6, size 8192, journal first block 18, max trans len 1024, max batch 900, max commit age 30, max t
rans age 30
ReiserFS: hda6: checking transaction log (hda6)
ReiserFS: hda6: Using r5 hash to sort names
ReiserFS: hda7: found reiserfs format "3.6" with standard journal
ReiserFS: hda7: using ordered data mode
ReiserFS: hda7: journal params: device hda7, size 8192, journal first block 18, max trans len 1024, max batch 900, max commit age 30, max t
rans age 30
ReiserFS: hda7: checking transaction log (hda7)
ReiserFS: hda7: Using r5 hash to sort names
ReiserFS: hda8: found reiserfs format "3.6" with standard journal
ReiserFS: hda8: using ordered data mode
ReiserFS: hda8: journal params: device hda8, size 8192, journal first block 18, max trans len 1024, max batch 900, max commit age 30, max t
rans age 30
ReiserFS: hda8: checking transaction log (hda8)
ReiserFS: hda8: Using r5 hash to sort names
ReiserFS: hda9: found reiserfs format "3.6" with standard journal
ReiserFS: hda9: using ordered data mode
ReiserFS: hda9: journal params: device hda9, size 8192, journal first block 18, max trans len 1024, max batch 900, max commit age 30, max t
rans age 30
ReiserFS: hda9: checking transaction log (hda9)
ReiserFS: hda9: Using r5 hash to sort names
Real Time Clock Driver v1.12
8139too Fast Ethernet driver 0.9.27
ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 10
PCI: setting IRQ 10 as level-triggered
ACPI: PCI interrupt 0000:00:0e.0[A] -> GSI 10 (level, low) -> IRQ 10
eth0: RealTek RTL8139 at 0xded90000, 00:50:fc:cd:88:dd, IRQ 10
eth0: Identified 8139 chip type 'RTL-8100B/8139D'
Forcing 10Mbps half-duplex operation.
ACPI: PCI Interrupt Link [LNKC] enabled at IRQ 9
PCI: setting IRQ 9 as level-triggered
ACPI: PCI interrupt 0000:00:07.5[C] -> GSI 9 (level, low) -> IRQ 9
PCI: Setting latency timer of device 0000:00:07.5 to 64
usbcore: registered new driver usbfs
usbcore: registered new driver hub
Initializing USB Mass Storage driver...
usbcore: registered new driver usb-storage
USB Mass Storage support registered.
USB Universal Host Controller Interface driver v2.2
ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 9
ACPI: PCI interrupt 0000:00:07.2[D] -> GSI 9 (level, low) -> IRQ 9
uhci_hcd 0000:00:07.2: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
uhci_hcd 0000:00:07.2: irq 9, io base 0xd400
uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 1
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
ACPI: PCI interrupt 0000:00:07.3[D] -> GSI 9 (level, low) -> IRQ 9
uhci_hcd 0000:00:07.3: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (#2)
uhci_hcd 0000:00:07.3: irq 9, io base 0xd000
uhci_hcd 0000:00:07.3: new USB bus registered, assigned bus number 2
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 2 ports detected
usb 1-2: new low speed USB device using uhci_hcd and address 2
usbcore: registered new driver hiddev
usb 2-2: new full speed USB device using uhci_hcd and address 2
scsi0 : SCSI emulation for USB Mass Storage devices
usb-storage: device found at 2
usb-storage: waiting for device to settle before scanning
input: USB HID v1.10 Mouse [Logitech USB Mouse] on usb-0000:00:07.2-2
usbcore: registered new driver usbhid
drivers/usb/input/hid-core.c: v2.0:USB HID core driver
Disabled Privacy Extensions on device c05d68a0(lo)
Vendor: USB MASS Model: STORAGE DEVICE Rev: 0.10
Type: Direct-Access ANSI SCSI revision: 02
Attached scsi removable disk sda at scsi0, channel 0, id 0, lun 0
usb-storage: device scan complete
eth0: no IPv6 routers present

The PC was indeed turned off between the two checks.
However the first check was not performed right before the shutdown, but few hours before it.
:idea:
(...) varying from browser cache data increase to a cronjob like updatedb, or even you installing or downloading something.
When I've read these words I have started to "scroll" back in my memory buffer and eventually I've remembered that the only thing I did as superuser was to download some Firefox extensions which (surprise or not...) summed up to ~12M.
So we have the answer for this one too thanks to your hints
PS: That's exactly the reason why I've made a small / partition - to keep a close eye on it's usage and to ring some allarms when needed.
Again, thank you.

Using DMA to update values in an array

Good afternoon,
I've been running into a few problems with my vi, and I'd like to give a bit of the background information before I ask my questions. I'm using Labview 8.5 and the NI USB-6009 DAQ. I want to use an encoder to control values that are being written to a file for DMA. I found that I couldn't use the encoder as an external clock since the 6009 DAQ doesn't have this capability. So I've been trying to go a differenet route by using a case structure with a True/false statement to allow me to input values from a simulated signal into a write vi (each time the encoder pulses, a value from the simulated signal should be inputed into the write data storage vi). From there, I want to then read those values and put them into an array. So the plan is to have a 10 element array that reads in values from the storage file (just like in FIFO for FPGA). As I continue reading values, the oldest value of the 10 element array will leave the array and be replaced by a new value.
Now here come the questions, I'm using the Write/Read data storage vi's and I keep getting errors. First, if I'm wanting to use DMA to read these values am I using the correct vi's, or is there a different route? Also, once I read these values into the array how would I be able to constantly update the array in a descending order from begining to end of the stored values?
I'm posting my most recent vi that I've been editing. Also, in advance, thank you!
-tjm
Attachments:
Using Encoder as an analog input 10_9_13 - Copy - Copy.vi ‏390 KB

Thank you for your reply.
First, I'm ultimately trying to use the array as input into a visual display for a meter (to display the mean of the array). I've been successful (in the past) with inputting into an array by not using DMA and using the Sort 1D Array point by point vi. The only problem is the timing mechanism with the encoder, and you are correct with stating that there is uncertainty with the encoder when trying to retrieve values from the input signal (sine wave). I thought about going down the route of using the encoder as a counter (since I am able to see the counter increase by a single digit with each pulse).
My question would then be how to control the case structure with a counter input?
I'm posting both my setup with the Sort 1D Array Point by Point and the simple vi for the encoder as a counter. My idea is to try to merge the two and have the counter control the case structure.
Is there a way I can do this?
Attachments:
Sort 1D Array Pt by Pt.vi ‏189 KB
Using Encoder as a counter input 10_9_13.vi ‏123 KB

MHDDK with Visa: event when DMA transfer complete?

We are using devices like PXIe-6363, PCIe-6321 depending on requirements and these are dealt with using the MHDDK with Visa backend on Windows (I hope that is the correct terminology).
All I/O, both analog and digital simultaneously, is done using DMA transfers using the standard MHDDK classes for doing so. This all works without problems.
One last improvement is I'd like to be notified using a callback/event system when a new block of data is ready: currently I'm just polling the input DMA's available number of bytes in a continuous loop with no sleep() in order to be able to process data as soon as it's ready. Works, but keeps one cpu busy the whole time.
I didn't see any way to use callbacks using the MHDDK which makes sense since it's purely based on register I/O if I understand it correctly.
However I noticed Visa has viInstallHandler, viEnableEvent and the likes. I went through some documentation on the event types but admit this is over my head and I have no idea where to start.
Could anyone point me in the right direction?
First question is if what I'm asking for is possible? Second I think I just have to call viInstallHandler for the correct event type, then figure out if the event is for an input DMA transfer from PXI? Using viGetAttribute somehow?
Thanks in advance!

You'll have better luck posting to the ddk board - http://forums.ni.com/t5/Driver-Development-Kit-DDK/bd-p/90

I want to check all functions of PCI 6534.I have read the user manual..I have some memory related questions.Please help me for that.

I want to check all functions of PCI 6534.I have read the user manual..I have some memory related questions.Please help me for that.
1.)If i am using the continuous output mode.and the size of generated data is less than 32 MB.If i want to preload the memory,what should i do?I want that first of all i load all my data to onboard memory & then i want to make start the transfer between 6534 & peripheral.Is it possible?As per me it should be.Plz tell me how should i do this?I think that in normal procedure the transfer between 6534-peripheral & outputting data from pc buffer to onboard memory works parallely.But i don't want this.Is it poss
ible?
(2).Similarly in finite input operation(pattern I/O) is it possible to preload the memory and then i read it?Because i think that the PC memory will be loaded automatically when 6534 acquires the data and then when we use DIO read vi the pc buffer data will be transferred to application buffer.If this is true,i do not want this.Is it possible?
(3) One more question is there if i am using normal operation onboard memory will be used bydefault right?Now if i want to use DMA and if i have data of 512 bytes to acquire.How will it work and how should i do it?Please tell me the sequence of operations.As per my knowledge in normal DMA operation we have 32 Bytes FIFO is there so after acquisition of 32 bytes only i can read it.How it will known to me that 32 bytes acquisition is complete?Next,If i want to acquire each byte separately using DMA interrupts what should i do?Provide me the name of sourse from which i can get details about onboard memory & DMA process of 6534 specifically
(4).In 6534 pattern Input mode,if i want to but only 10 bits of data.and i don't want to waste any data line what should i do?

Hi Vishal,
I'll try to answer your questions as best I can.
1) It is definitely possible to preload data to the 32MB memory (per group) and start the acquisition after you have preloaded the memory. There are example programs on ni.com/support under Example Code for pattern generation and the 6534 that demonstrate which functions to use for this. Also, if your PC memory buffer is less than 32MB, it will automatically be loaded to the card. If you are in continuous mode however, you can choose to loop using the on-board memory or you can constantly be reading the PC memory buffer as you update it with your application environment.
2) Yes, your data will automatically be loaded into the card's onboard memory. It will however be transferred as quickly as possible to the DMA FIFO on the card and then transferred to the PC memory buffer through DMA. It is not going to wait until the whole onboard memory is filled before it transfers. It will transfer throughout the acquisition process.
3) Vishal, searching the example programs will give you many of the details of programming this type of application. I don't know you application software so I can't give you the exact functions but it is easiest to look at the examples on the net (or the shipping examples with your software). Now if you are acquiring 512 bytes of data, you will start to fill your onboard memory and at the same time, data will be sent to the DMA FIFO. When the FIFO is ready to send data to the PC memory buffer, it will (the exact algorithm is dependent on many things regarding how large the DMA packet is etc.).
4) If I understand you correctly, you want to know if you waste the other 6 bits if you only need to acquire on 10 lines. The answer to this is Yes. Although you are only acquiring 10 bits, it is acquired as a complete word (16bits) and packed and sent using DMA. You application software (NI-DAQ driver) will filter out the last 6 bits of non-data.
Hope that answers your questions. Once again, the example code on the NI site is a great place to start this type of project. Have a good day.
Ron

Cd burner issues with Nero, Atapi and DMA

Hello,
When i first build my AMD system with the specs below, everything was mostly fine on the IDE drive topic. Nero was burning fine, Alcohol 120 was working etc etc...
Recently when i decided to format my computer, things started to fail.
The OS install went fine, all drivers installed just fine with the exception of the NVidia SW drivers. When I opt to install these drivers, whether it be v 5.03, or 5.10, the system will hang if I insert a cd into the cd rom drive. It attempts to read, then the system will totally hang.
If these were uninstalled, it would work flawlessly. But that is off topic.
What i've read in these threads is that if I select to use PIO and not DMA on the cd rom ide channels in windows/bios, the burner would fine with Nero. With DMA turned on, the program will hang during the 'checking discs' window just before the burnging process begins. The burner doesnt even attempt to see the cdr in the drive.
But my question is, does anyone know why some of us need to disable DMA for the IDE drives/channels for it to work? I've read others were having problems reading from DVD drives etc with DMA enabled. Disabling DMA and using PIO only would see the DVD drive work fine.
Is this a known issue with the board or drivers?
BTW: I have 2 hdds on primary channel, and the single burner on the 2ndary channel as mater. Burner is an old Kodak/Mitsumi 4xCD burner, 2xCDRW.
Your thoughts will be much appreciated..
Many thanks.

Got some more information based on the advice on this thread.
I tried removing all the 12 IDE ATA/ATAPI Controllers, and once rebooted, winxp would fail to startup.
So I restarted with the last known working settings, then I narrowed it down to the middle one of each of the channels to be the most important.
- Primary IDE Channel 1
- Primary IDE Channel 2
- Primary IDE Channel 3
- Secondary IDE Channel 1
- Secondary IDE Channel 2
- Secondary IDE Channel 3
- Standard Dual Channel PCI IDE Controller 1
- Standard Dual Channel PCI IDE Controller 2
- Standard Dual Channel PCI IDE Controller 3
After removing all 1 and 3's. A 'scan for hardware' change automatically detected them again and automatically installed them again with the MS drivers.
I have also tried the end ide connection from the 3 connector ide cable I was using, and still no luck.
Channel 0 with both the hdds installed are using the red round ide cable. While Channel 1 with the single burner is installed with the standard flat grey ide cables.
Bagmaster: This is the funny thing though. When i first built the computer, the burner was working absolutely fine with Nero. It wasn't until I format the computer and decided to use 5.10 drivers that it gave me problems. I then did another format with the old 5.03 drivers and yet, still no luck...
The problem mysteriously popped up after the format, and just doesn't want to go away.
tomkas: I may attempt your idea. I will let you know what comes from it. Hope it doesn't force me to make yet another format of the system.. I have done once too many on this computer than I'd done for my old Intel system for 4 years...
syar2003: Hmm, i'm not quite sure if these grey ide cables are 40 or 80pins. I've been using these since the early 2000's with my intel computer. Heck, i didn't even know they upped the pins?? I thought ide cables fit all new and old drives [whether they be hdd or cd drives]

File permission error; NI-488: DMA hardware error detected

I'm running LabVIEW 8.0 on the latest supported SUSE linux. My vi saves a data file. If I save a file named "/home/bill/LabVIEW/data/file.dat," it saves okay the first time. But then if I run the program again, it gives me an error instead of just writing over file.dat (which is what I want it to do).
Error 8 occurred at Open/Create/Replace File in filename.vi
Possible reason(s):
LabVIEW: File permission error.
NI-488: DMA hardware error detected.
Also, I don't know if this is related, but when I click on the folder icon to the right of the file path on the front panel, and navigate to the directory mentioned above, then type "file.dat," I get the message "/home/bill/LabVIEW/data/file.dat does not exist." Shouldn't this *create* the new file?
Thanks,
Bill

You should really start your own thread describing your problem in detail. One of the issues here is that there are two possible sources for the error code 8. Which one is applicable to you? What platform are you on? What version of LV? What are you trying to accomplish? What exactly triggers the error?
Please start again with your own thread and with the answers the questions I asked (as well as anything else that you think might be of value).
Mike...
Certified Professional Instructor
Certified LabVIEW Architect
LabVIEW Champion
"... after all, He's not a tame lion..."
Be thinking ahead and mark your dance card for NI Week 2015 now: TS 6139 - Object Oriented First Steps

Dma timeout

Hello Vitaly Filatov,
It looks like you did not get my response to your questions because I had some trouble loggin in to the sun forum. So I am posting it again.
thanks
Aspiration
thank you for your response. Here is the info you wanted.
On Ultra 60 (where my driver works fine)
uname -srvmpi produces the following output:
SunOS 5.9 Generic_117171-07 Sun4u sparc sunw, ultra-60
and .version proudces the following output:
Release 3.31 Version 0 created 2001/7/25 20:31
OBP: 3.31.0 2001/7/25 20:31
POST: 2.0.3 2000/7/31 15:28
On Sunblade 2500 where my driver crashes, uname produces
sunos 5.9 Generic_117171-07 sun4u sparc sunw, sun-blade-2500
and .version produces
Release 4.13.5 created 2004/5/27 17:31
OBP: 4.13.5 2004/5/27 17:31 sunblade 2500, sunfire v250
OBDIAG: 4.13.5 2004/5/27 17:33
POST: 4.13.0 2004/1/16 12:39
Please note that due to the very high speed acquisition rate of the ADC board, DMA is used to transfer data from ADC onboard memory to user space.
thanks
Aspiration

I'm having the same problem. My scanner is a HP ScanJet 8250. I'm using Adobe Pro Extended & Windows Fax & Scan programs. Currently running Windows 7 (64 bit) Professional on an Intel i7-2600 CPU with 4x2.00GB of DDR3-1333 RAM
When using the feeder tray, it will either feed 3/4 of a page before timing out or it will not scan anything at all. When using the flatbed, the scanning bulb will move down the glass but then stop at the end and timeout.
I did have this scanner fuctioning properly on another computer using Windows 7 (64 bit) Ultimate but the hardware specs elude me at this point in time. I saw there was a firmware update for previous generations of Windows but nothing for Windows 7.
So far I have tried uninstalling & reinstalling the driver. Switching through every USB port on the tower. And I've swapped out the USB cable.
Any help would be greatly appreciated.

DMA RT to FPGA guaranteed order?

I have a question regarding the sending of data via FIFO to an FPGA card via DMA. I would assume that if I have several locations in my RT code sending data via DMA FIFO that it is still guaranteed that any given DMA Transfer (let's say 12 data values) are delivered atomically. That is to say that each DMA node data is sent as a contiguous block.
Take the following example. I have two DMA FIFO nodes in parallel. I don't know which is going to be executed first, and they will most of the time be vying for bandwidth. Both nodes send over the SAME DMA FIFO. Does the data arrive interleaved, or is each sent block guaranteed to be contiguous ont he receiving end. Do I end up with
Data0 (Faster node)
Data1 (Faster node)
Data2 (Faster node)
Data3 (Faster node)
Data11 (Faster node)
Data0 (Slower node)
Data1 (Slower node)
Data11 (Slower node)
or do the individual items get interleaved.
I'm kind of assuming that they remain in a contiguous block which I'm also hoping for because I want to abuse the DMA FIFO as a built-in timing source for a specific functionality I require on my FPGA board. I can then use the RT-FPGA DMA Buffer to queue up my commands and still have them execute in perfect determinism (Until the end of the data in my single DMA transfer of course).
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant

Woah, new avatar. Confusing!
I am going to preface this by saying that I am making assumptions, and in no way is this a definitive answer. In general, I have always had to do FPGA to RT streaming through a FIFO and not the other way around.
When writing to the FPGA from the RT, does the FIFO.write method accept an array of data as the input? I'm assuming it does. If so, I'd then make the assumption that the node is blocking (like most everything else in LabVIEW). in which case the data would all be queued up contiguously. Interleaving would imply that two parallel writes would have to know about each other, and the program would wait for both writes to execute so that it could interleave the data. That doesn't seem possible (or if it was, this would be an awful design decision because what if one of the writes never executed).
Of course, this is all assuming that I am understanding what you are asking.
You're probably safe assuming the blocks are contigous. Can you test this by simulating the FPGA? If your'e really worried about interleaving, could you just wrap the FIFO.write method up in a subVI, that way you are 100% sure of the blocking?
Edit: Had a thought after I posted, how can you guarantee the order things are written to the FIFO? For example, what if the "slow" write actually executes first? Then your commands, while contiguous, will be "slower node" 1-12 then "faster node" 1-12. It seems to me you would have to serialize the two to ensure anything.
Sorry if I'm not fully understanding your question.
CLA, LabVIEW Versions 2010-2013

DMA "Acquire Read Region" method

I've been meaning to ask this question for a while now.
I just came across the FPGA method mentioned in the title of this post. I understand it gives a DVR pointing to the actual memory range for a DMA transfer but I have some questions regarding the implementation.
Does the function to return the DVR only return when the requested memory space is available AND the requested number of elements are already present?
Can this be used to speed up DMA transfer between loops?
Shane
Edit: What i mean by speeding up transfers between loops is the following: I would like to have the DMA read outside my time critical loop on RT and passing the data in via FIFO or QUEUE but when I try to do this with a standard DMA FIFO read, I get some not very good performance and a lot of jitter. I am hoping this new method might be a step in improving that situation.
Say hello to my little friend.
RFC 2323 FHE-Compliant

There is method to my insanity.
We have an application where wa are running a RT loop at 20kHz including DMA transfers (25kHz is possible but with more jitter). When looking at the RT execution trace toolkit we see that the DMA transfers are actually making up a rather large portion of our loop times. The idea was to offload the actual DMA transfer to a seperate CPU core in order to allow for a data transfer method with a lower minumum runtime.
In our case our DMA transfers are taking approximately 10 us per call which actually ends up liniting our maximum loop rate "artiificially". We have DMA transfers in both directions, so in essence we lose 20us through the DMA transfers. Of course having the DMA transfer in the timed loop is great for jitter but the maximum loop rate is lower than it theoretically could be if the data transfer between RT and FPGA was faster.
I had a system up and running with the DMA transfers offloaded to a seperate CPU core but the jitter was too high. I was hoping the ability to pass a DVR instead might help things in this regard.
Is there any way of offloading the DMA transfers in this way, essentially "pipelining" the DMA transfers to allow for higher RT Loop rates but without introducing some nasty jitter?
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant

Downcasting DMA data from U16 to U8

Hi Everyone,
I have a situation that I hope someone can shed some light on. Currently I have an FPGA design that collect highspeed data does some processing on it and spits out the results over DMA for the host to read out and save to TDMS files. Currently I am reading 4MB worth of I16 data from the DMA every 25-30 ms, the current design is able to keep up with the data rate just fine. My next task is to allow the FPGA to collect the same type of data, with the same processing, only providing the data back in I8 format, which means one of the following design decisions:
1- keep existing FPGA code/FW and cast the data to I8 on the host side.
The downside to the first option, is the high data rate. I did some benchmark testing with a couple of different methods to do the I16 to I8 cast (Number Split, to I8 cast, and Typecast). Needless to say the Typecast was too slow for my operations averaging about 35-40 ms to cast the 4MB worth of I16 data to I8. The number split and to I8 cast both came with an average time of approximatly 15ms but with a max time of 23 ms. These times were obtained with a system with very little load, which will not be the case on the final design.
2- develop/compile a new FPGA VI that does the exact same operations except convert the data to I8 on the FPGA and send it over a DMA defined with I8 datatype.
The downside here is the need to maintane two versions of the FPGA code as well as two versions of the driver code, this is since the DMA used to transfer the data has changed datatype from I16 to I8 which prevents me from using a dynamic refrence when operating with the FPGA. I also am using all the available DMA channels on board so I cannot just declare both I16 and I8 DMAs and read from the appropriate one on the driver side.
My question is, is there a cheap way of doing the cast operation on the host side? It was mentioned that LV FPGA will use U64 to transfer the data internally and only cast it to the required data type at the end, is it possible to leverage this operation to get it to cast to a differnt data type on the driver side, if this is true? Otherwise is there a fourth method of doing the cast that is cheaper? any other ideas are welcome.
Sorry for the long post.
Solved!
Go to Solution.

Update your FPGA to be configurable to either pack I16s or I8 into its DMA stream, that way you have one FPGA to maintain and you have a reduced stream from the I8 configured FPGAs (i.e. half the number of DMA values should be sent). Send your DMA values to always be some multiple of I16 so you can easily pack and unpack once they are in TDMS files. The host side always receives the same DMA element (e.g. I16) and doesn't really care that in some cases it contains two I8s.

How can i decide the depth of all3 DMA fifo's are used as target to host at RT contoller side(host)?

Hello,
I am using all DMA fifos,I want to acquire data from 3 AI modules upto 50 khz frequency.Sampling rate can be varied according to application.
please suggest me how should i allocate memory of my RT controller for those DMA fifos?I am also facing one problem, I am using 3 time deterministic loop with different different priorities,each time loop has one fifo where data is reading with polling method(first fifo.read=0 then againg fifo.read=remaining elements).and each time loop has been interact to host vi with global varibales.those global variables data update from normal time loop.can anybody suggest that this procedure is right or not.if my problem is not much clear i will again explaing my query with snapshot of my application.
Pratima
*****************Certified LabView Associate Developer****************************

You wouldnt need to allocate memory separately on your RT Controller for the FIFOs. You need to create a FIFO under your FPGA target and use the FPGA interface VIs in your RT VI to access the DMA FIFO. You would need to use the FPGA interface invoke method VI to access your DMA FIFO.
As for the other questions, I would recommend you to create a separate post the RT section of LabVIEW so that you can get a faster response to your questions.
I hope this helps!
Mehak D.

Data transfer from RT to FPGA using DMA FIFO

Hello all,
My question is "How do you stream data from RT target to FPGA target using DMA FIFOs?"
I would like to control some indicators (or controls) in FPGA vi using controls in the RT vi using DMA FIFO.
I have used four controls in my RT vi, but I get only one indicator out on my FPGA vi. (I would actually like to use some controls on the FPGA target using controls on the RT target)
Is this possible?
Can anyone help me with this?
I have attached my vi s.
Attachments:
fpgatest.vi ‏28 KB
rt_test.vi ‏73 KB

Based purely on your example, I see two options:
1. Do as RavensFan suggests and use Boolean Array To Number to send a single number down to the FPGA. Your FPGA can break up the number easily enough to update the indicators.
2. Just write dirctly to the indicators. I do not see a need for the DMA. Again, based purely on your example.
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