DMA RT to FPGA guaranteed order?

I have a question regarding the sending of data via FIFO to an FPGA card via DMA. I would assume that if I have several locations in my RT code sending data via DMA FIFO that it is still guaranteed that any given DMA Transfer (let's say 12 data values) are delivered atomically. That is to say that each DMA node data is sent as a contiguous block.
Take the following example. I have two DMA FIFO nodes in parallel. I don't know which is going to be executed first, and they will most of the time be vying for bandwidth. Both nodes send over the SAME DMA FIFO. Does the data arrive interleaved, or is each sent block guaranteed to be contiguous ont he receiving end. Do I end up with
Data0 (Faster node)
Data1 (Faster node)
Data2 (Faster node)
Data3 (Faster node)
Data11 (Faster node)
Data0 (Slower node)
Data1 (Slower node)
Data11 (Slower node)
or do the individual items get interleaved.
I'm kind of assuming that they remain in a contiguous block which I'm also hoping for because I want to abuse the DMA FIFO as a built-in timing source for a specific functionality I require on my FPGA board. I can then use the RT-FPGA DMA Buffer to queue up my commands and still have them execute in perfect determinism (Until the end of the data in my single DMA transfer of course).
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant

Woah, new avatar. Confusing!
I am going to preface this by saying that I am making assumptions, and in no way is this a definitive answer. In general, I have always had to do FPGA to RT streaming through a FIFO and not the other way around.
When writing to the FPGA from the RT, does the FIFO.write method accept an array of data as the input? I'm assuming it does. If so, I'd then make the assumption that the node is blocking (like most everything else in LabVIEW). in which case the data would all be queued up contiguously. Interleaving would imply that two parallel writes would have to know about each other, and the program would wait for both writes to execute so that it could interleave the data. That doesn't seem possible (or if it was, this would be an awful design decision because what if one of the writes never executed).
Of course, this is all assuming that I am understanding what you are asking.
You're probably safe assuming the blocks are contigous. Can you test this by simulating the FPGA? If your'e really worried about interleaving, could you just wrap the FIFO.write method up in a subVI, that way you are 100% sure of the blocking?
Edit: Had a thought after I posted, how can you guarantee the order things are written to the FIFO? For example, what if the "slow" write actually executes first? Then your commands, while contiguous, will be "slower node" 1-12 then "faster node" 1-12. It seems to me you would have to serialize the two to ensure anything.
Sorry if I'm not fully understanding your question.
CLA, LabVIEW Versions 2010-2013

Similar Messages

Dma host to fpga

Use the DMA to transfer a array data from the RT system to the FPGA,and indicate the array data in the FGPA.
Now,If the array data in the RT is a array including one element ,Ican recevie well in the FPGA VI,bcause in the FPGA VI the function of DMA Read only accept the single element,you can not put a array indication .But I want to transfer a array including many elements.How can i do?

Hi,
You must use only fixed-size arrays in FPGA VIs. If you have a For Loop without a set number of iterations, you must use a Numeric Constant or a control to set the number of iterations. Alternatively, if you are building an array by using the Insert Into Array function, substitute with the Replace Array Subset function.
I don’t know if this solve your problem, if not attach your VI and I goanna see what’s happen.
Hope this helps,
Benjamin R.
R&D Software Development Manager
http://www.fluigent.com/

Need fast, efficient, open-source PCIe DMA for your FPGA? RIFFA 2.2 from UCSD goes on GitHub

PCIe has been an intra-system connection interface of choice for quite a while now, offering a standardized and well-understood way to move large amounts of data quickly between, for example, a host CPU and an FPGA. Efficient, high-speed PCIe screams for DMA and if that’s what you need, the latest version of RIFFA 2.2 (Reusable Integration Framework For FPGA Accelerators) is now posted on GitHub and includes DMA IP you might want for your current or your next design.
RIFFA 2.2 employs communication channels between software threads running on a CPU and hardware user cores instantiated on an FPGA. A channel is similar to a network socket in that it must be opened before it can be read and written. Then it must be closed. However, unlike a network socket, channel reads and writes be made simultaneous by using two threads. Each channel is independent and thread-safe. RIFFA 2.2 supports as many as twelve channels.
Here’s a block diagram of the RIFFA hardware/software architecture:
RIFFA Hardware/Software Architecture
But the real measure of a DMA controller is its ability to move data quickly and efficiently. According to the UCSD RIFFA Web page, the latest RIFFA versions are “able to saturate the PCIe link for nearly all link configurations supported.” The following chart shows the performance of designs based on RIFFA 2.1 using the 32 bit, 64 bit, and 128 bit interfaces:
For more detailed information about RIFFA, see the RIFFA 2.2 documentation and these two papers:
RIFFA: A Reusable Integration Framework for FPGA Accelerators
RIFFA 2.0: A Reusable Integration Framework for FPGA Accelerators

Hi,
I'm from germany so no 'best buy' but I think I will lock around sleeve/bag for a different product with same measures. Any tip?
The clear plastic case is not what I want. I would like to use the player without such protections. I just want a sleeve to protect the player while its in my jacket/pants.
Btw, i have bought this version: Creative Zen (maybe european version?). I also doesn't seem to have your mentioned sleeve. I also couldn't find it on the website.
Anyway, thank you,
Chris

Probleme mit dem Lesen von DMA FIFOs vom FPGA!

Attachments:
burstgen_digital_input_2emitter.zip ‏2288 KB

Hi, please do not post code without any comment!
Please provide some kind of description. thx
M. Brauner NIG

Most efficient data transfer between RT and FPGA

This post is related to THIS post about DMA overhead.
I am currently investigating themost efficient way to transfer a set of variables to a FPGA target for out application. We have been using DMA FIFOs for communications in both directions (to and from FPGA) but I'm recently questioning whether this is the most efficient approach.
Our application must communicate several parameters (around 120 different variables in total) to the FPGA. Approximately 16 of these are critical meaning that they must be sent every iteration of our RT control loop. The others are also important but can be sent at a slightly slower rate without jeopardising the integrity of our system. Until now we have sent these 16 critical parameters plus ONE non-critical parameter over a DMA to the FPGA card. Each 32-bit value sent incorporates an ID which allows the FPGA to demultiplex to the appropriate global variables on the FPGA. Thus over time (we run a 20kHz control loop on the RT system - we have a complete set of paramaters sent @ approx. 200Hz). The DMA transfers are currently a relatively large factor in limiting the execution speed of our RT loop. Of the 50us available per time-slot running at 20kHz approximately 12-20us of these are the DMA transfers to and from the FPGA target. Our FPGA loop is running at 8MHz.
According to NI the most efficient way to transfer data to a FPGA target is via DMA. While this may in general be true, I have found that for SMALL amounts of data, DMA is not terribly efficient in terms of speed. Below is a screenshot of a benchmark program I have been using to test the efficiency of different types of transfer to the FPGA. In the test I create a 32MB data set (Except for the FXP values which are only present for comparison - they have no pertinence to this issue at the moment) which is sent to the FPGA over DMA in differing sized blocks (with the number of DMA writes times the array size being constant). We thus move from a single really large DMA transfer to a multitude of extremely small transfers and monitor the time taken for each mode and data type. The FPGA sends a response to the DMA transfers so that we can be sure that when reading the response DMA that ALL of the data has actually arrived on the FPGA target and is not simply buffered by the system.
We see that the minimum round-time for the DMA Write and subsequent DMA read for confirmation is approximately 30us. When sending less than 800 Bytes, this time is essentially constant per packet. Only when we start sending more than 800 Bytes at a time do we see an increase in the time taken per packet. A packet of 1 Byte and a packet of 800 Bytes take approxiamtely the SAME time to transfer. Our application is sending 64 Bytes of critical information to the FPGA target each time meaning that we are clearly in the "less efficient" region of DMA transfers.
If we compare the times taken when communication over FP controls we see that irrespective of how many controls we write at a time, the overall throughput is constant with a timing of 2.7us for 80 Bytes. For a small dedicated set of parameters, the usage of front panel controls seems to be significantly faster than sending per DMA. Once we need to send more than 800 Bytes, the DMA starts to become rapidly more efficient.
Say hello to my little friend.
RFC 2323 FHE-Compliant

So to continue:
For small data sets the usage of FP controls may be faster than DMAs. OK. But we're always told that each and every FP control takes up resources, so how much more expensive is the varsion with FP controls over the DMA.
According to the resource usage guide for the card I'm using (HERE) the following is true:
DMA (1023 Elements, I32, no Arbitration) : 604 Flip-Flops 733 LUT 1 Block RAM
1x I32 FP Control: 52 Flip-Flops 32 LUTs 0 Block RAM
So the comparison would seem to yield the following result (for 16 elements).
DMA : 604 FLip-Flops 733 LUT 1 Block RAM
FP : 832 FLip-Flops 512 LUT 0 Block RAM
We require more FLip-Flops, less LUTs and no Block RAM. It's a swings and roundabouts scenario. Depending on which resources are actually limited on the target, one version or the other may be preferred.
However, upon thinking further I realised something else. When we use the DMA, it is purely a communications channel. Upon arrival, we unpack the values and store them into global variables in order to make the values available within the FPGA program. We also multiplex other values in the DMA so we can't simply arrange the code to be fed directly from the DMA which would negate the need for the globals at all. The FP controls, however, ARE already persistent data storage values and assuming we pass the values along a wire into subVIs, we don't need additional globals in this scenario. So the burning question is "How expensive are globals?". The PDF linked to above does not explicitly mention the difference in cost between FP controls and globals so I'll have to assume they're similar. This of course massively changes the conclusion arrived to earlier.
The comparison now becomes:
DMA + Globals : 1436 Flip-Flops 1245 LUTs 1 Block RAM
FP : 832 FLip-Flops 512 LUT 0 Block RAM
This seems very surprising to me. I'm suspiscious of my own conclusion here. Can someone with more knowledge of the resource requirements differences between Globals and FP controls weigh in? If this is really the case, we need to re-think our approach to communications between RT and FPGA to most likely employ a hybrid approach.
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant

What is the order of Column Names in Sqlite query results?

I am writing an application using Adobe Air, Sqlite, and Javascript.
After writing the following select statement:
          SELECT field1, field 2, field 3, field 4 FROM TableA;
I would like to get the columnName/data combination from each row -- which I do successfully with a loop:
          var columnName="";
          for (columnName in selResults.data[i]) {
               output+=columnName + ":" + selResultsdata[i][columnName] + ";";
My issue is that the column names come out in a different order every time I run the query and never once have they come out in the desired order -- field 1, field 2, field 3, field 4. If I run the query in Firefox's Sqlite Manager, the columns come out in the "proper" order. When I run them in Adobe Air, the order will be the same if I run the query mulitple times without closing the app. If I make a change such as declaring the columnName variable with "" before the for column, or declare it as (var = columnName in selResults.data) , then the order changes. If I shut down my app and re-open after lunch and run query, it comes out in another order. At this time, I'm not interested in the order of the rows, just the order of the columns in each output row. I've even tried assiging an index to columnName which seems to just pick up a single letter of the columnName.
I'm in the process of changing my HTML presentation of the data to assign a precise columnName to an HTML table title, but I'm reluctant to let go of the above concept as I think my separation of HTML/presentation and Javascript would be better if I could use the solution described above.
So, does anybody know how to force the order of the columnNames in my output -- or what I'm doing to cause it to come out in a different order?
Jeane

Technically there isn't any "order" for the return columns. They aren't returned as an Array -- they're just properties on an Object instance (a "generic object"). The random order you're seeing is the behavior of the for..in loop iterating over the properties of the object. Unfortunately, with a for..in loop there is no guaranteed order for iterating over properties (and, as you've seen, it tends to vary wildly).
The only solution is to create your own list of the column names and sort it the way you want to, then use that to create your output. For example, use the for..in loop to loop over the properties, but rather than actually get the values, just dump the column names into an Array:
var columnName="";
var columns = [];
for (columnName in selResults.data[i]) {
    columns.push(columnName);
columns = columns.sort(); // just uses the default alphabetical sort -- you would customize this if desired
var j = 0;
for (j = 0; j < columns.length; j++) {
    columnName = columns[j];
    output+=columnName + ":" + selResultsdata[i][columnName] + ";";

Problem with ordering in select query.

Hi,
We have the following query:
SELECT s.surveyid, m.messageid, m.text FROM MS_SURVEY s, MS_MESSAGES m where (m.messageid=s.survey_desc or m.messageid=s.survey_heading or m.messageid=s.user_profiles) and s.surveyid=xxx
This query selects 3 rows, one for description, one for heading and one for user profiles.
The problem is that, we have 4 databases. 2 Oracle 8.1.5, one Oracle 8.1.6 and one 8.1.7
This query when run on 8.1.7 and 8.1.5 will give us the result in the order:
1...description
2...heading
3...user profile
But, when run on 8.1.6 (which is the client setup of oracle)
The result is in the order:
1...user profile
2...heading
3...description
This project has still not been delivered because of this problem and we are already late by 2 months.
Please somebody let me know why this is happening?
I cannot change the code...as it has been tested for 1 month on staging setup, where it is working fine.
I have no clue as to why this is happening on the Client setup ONLY.
Is it a problem of different oracle versions, or any client side db trigger is there, or any options which the client has selected during his/her db installation or whatever...?
Kindly help.
Thank you.
Regards,
- Ram

Your query has no ORDER BY clause. Oracle does not guarantee (nor does any other RDB that I know of) to return rows in any particular order in the absence of an ORDER BY.
There are many factors that could affect the order in which rows will be returned in the absence of an eplicit ORDER BY clause. Among these are things like order of insertion of rows, access path chosen by the optimizer, the shoe size of the requestor.
You are going to have to change your code if you want a guaranteed order of the records.
TTFN
John

Select one of several FPGA VIs at runtime under RT program control

I need a CRIO RT controller to select one of several FPGA VIs (or bitfiles) at runtime based on an operating mode parameter.
The application requires the FPGA to acquire and process data using several different techniques based on a user supplied mode parameter. Each individual technique will fit into the FPGA, but there is not enough room to fit all of the techniques into the FPGA at the same time. Therefore, I need a way to programmatically select one of the FPGA VIs or bitfiles at runtime. The processed data is transferred to the RT through a common DMA FIFO, and all controls and I/O can be the same for each of the VIs.
I tried using a Case Structure on the RT to select the appropriate Open FPGA VI Reference call based on the current operating mode. When I wired the RefNum output from each case to the common output tunnel, I got an error stating that the RefNums were of different types.
I then tried binding the Open FPGA VI Reference calls to TypeDef or StrictTypeDef controls. In both cases there was an error stating that some of the Open FPGA VI Reference calls were bound to a TypeDef control which had changed.
Is it possible to select an FPGA VI or bitfile at runtime?
If not, is there a way to force the FPGA compiler to layout multiple VIs with the same interface structure so that the RT VI doesn't care which version is running?
If not, any suggestions short of duplicating the entire RT VI for each FPGA instance?
Thanks!

JohnZ wrote:
Is it possible to select an FPGA VI or bitfile at runtime?
Yes, using the FPGA Open VI Reference function as you are already doing, but you need a separate Open FPGA VI reference for each version of the FPGA VI or bitstream.
If not, is there a way to force the FPGA compiler to layout multiple VIs with the same interface structure so that the RT VI doesn't care which version is running?
No, the FPGA VI reference for each FPGA VI will be unique due to information about the interface and VI that is stored as part of the reference. If you are not using DMA in the FPGA VI, then you can use the Upcast function to convert the FPGA Reference into a more generic form which can be used interchangably with other FPGA references that have the same front panel configuration.
If not, any suggestions short of duplicating the entire RT VI for each FPGA instance?
Unfortunately no.
Christian Loew, CLA
Principal Systems Engineer, National Instruments
Please tip your answer providers with kudos.
Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
or for use in hazardous environments. You assume all risks for use of the Code and use of the Code is subject
to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense

TSQL verify sort order / UNION ALL

CREATE PROCEDURE Test
AS
BEGIN
SELECT * FROM (
SELECT 1 AS a,'test1' as b, 'query1' as c
UNION ALL
SELECT 2 AS a,'test22' as b, 'query22' as c
UNION ALL
SELECT 2 AS a,'test2' as b, 'query2' as c
UNION ALL
SELECT 3 AS a,'test3' as b, 'query3' as c
UNION ALL
SELECT 4 AS a,'test4' as b, 'query4' as c
) As sample
FOR XML RAW
END
Can we guarantee that the stored procedure returns results in given order?
Normally it says when we insert these select query to temporary table we can't guarantee its inserting order. So we have to use order by clause. But most of time it gives same order. Can we enforce to give it some different order? Is this related with clustered
and non clustered indices.
In second case can we enforce inserting order by adding Identity column?
Explain more on behind logic as well. I'm checking whether I need to add ORDER BY in old Stored Procedures or not.

Can we guarantee that the stored procedure returns results in given order?
No. The only way to get a guaranteed order is to use an ORDER BY clause.
Normally it says when we insert these select query to temporary table we can't guarantee its inserting order. So we have to use order by clause. But most of time it gives same order. Can we enforce to give it some different order? Is this related with
clustered and non clustered indices.
The only way to get a guaranteed order is to use an ORDER BY clause. Anything else is happenstance.
In second case can we enforce inserting order by adding Identity column?   Explain more on behind logic as well. I'm checking whether I need to add ORDER BY in old Stored Procedures or not.
Again: the only way to get a guaranteed order is to use an ORDER BY clause.
Erland Sommarskog, SQL Server MVP, [email protected]

Group By .. Order Results in Oracle 8i

Oracle 9i (9.2) makes statement that 'Group by does not guarantee order of results .. use Order by to sort results'.
Does this mean that under prior releases, esp. 8.1.7, that 'Group by' provides the proper Sort order of the results?
Or is 9.2 documentation, just clarifying what has always been the case?

Here is some information from the 8.1.7 SQL reference.
Use the order_by_clause to order rows returned by the statement. Without an order_by_clause, no guarantee exists that the same query executed more than once will retrieve rows in the same order.

How to achieve the order base on my input?

Hi all,
I have the following query
select column_name,column_id from user_tab_columns
             where table_name = 'ITEM_GROUPS'
               And column_id in (Select to_number(column_value) from The(Select cast(str2tbl('25,26,31,32,24') as mytabletype) from dual))I passing the input to str2tble function like the above examble ('25,26,31,32,24'). But when i run the above query,
i receiving the following output.
1     TYPE      24
2     MOC1     25
3     MOC2     26
4     SIZE1     31
5     SIZE2     32But i need the output based on the my input order. like
1     MOC1     25
2     MOC2     26
3     SIZE1     31
4     SIZE2     32
5     TYPE             24Please help me how to achieve this.
kanish

Off topic, but why aren't you just doing this:
select column_name,column_id
from user_tab_columns
where table_name = 'ITEM_GROUPS'
and column_id in (25,26,31,32,24)If you want a guaranteed order, then you will have to specify and ORDER BY.
For instance this one (though I don't expect that this is what you are looking for).
order by
case column_id
   when 25 then 1
   when 26 then 2
   when 31 then 3
   when 32 then 4
   when 24 then 5
endYou might try this (not tested):
select c.column_name,c.column_id
from user_tab_columns c
     ,(select to_number(column_value) as col_id
             ,rownum as rn
       from The(Select cast(str2tbl('25,26,31,32,24') as mytabletype) from dual) x
where c.table_name = 'ITEM_GROUPS'
and c.column_id = x.col_id
order by x.rnEdited by: Toon Koppelaars on Apr 27, 2011 12:53 PM

Can't make RT use generic FPGA FIFO

Hi all,
On a cRIO, I'm making a TCP server in RT that feeds data to a DMA FIFO for FPGA consumption. We are setting up multiple servers where each feeds a different DMA. (No, I don't want to merge and multiplex to single DMA).
I want a single RT program that takes a FIFO reference so that I can reuse the same RT code for different FIFOs. I can define a FPGA FIFO reference control,
but this only supports writing a single element at a time (or two on our target if you select peer-to-peer streaming for the FIFO). I have tuned the RT program for performance, and looping over thousands of elements per second in RT is NOT the solution. I want to use the "other" FIFO write which supports arrays - the one I can reference from an FPGA reference as follows:
However, using the FPGA reference I believe requires a particular named FIFO - therefore tying the RT code to a particular FIFO.
Any ideas how to do this?
Steve

All,
Thanks for the advice. I'm trying to create a basic test using the Advance Sessions Sources and am getting a FIFO name error (-61206) from the Get Single Resource Session node. The messy diagram below is showing the test VI on the right and a client VI on the left. The idea is to pass an FPGA reference and the FIFO name "FpgaDataIn" and the test VI grabs the FIFO by name and writes to the FIFO.
One issue to overcome is my beginner skills: the passed FPGA reference needs to be compatible with the FPGA reference control - which defeats the purpose of supporting generic FPGA references. There must be a way to specifiy a control that accepts a generic FPGA reference (dynamic FPGA cast? (which I've never used)).
Putting that issue aside for a moment, even when I define a FPGA reference control with a signature compatible with the passed FPGA reference I still get the 61206 error. I noticed issues related to upper/lower case and tried everything lower case (I THINK - I'm not positive I did it completely - but it's tedious with the FPGA reference signatures).
I read how the Get Single Resource Session needs a constant reference with a single "FIFO" fifo and have that.
Any tips?
Thanks!
Steve

Ordered processing required from Oracle 11g on Linux to BizTalk Server

Need a viable solution enabling ordered processing (OP) of messages from Oracle 11g on Linux allowing for ordered delivery to subscribers in BizTalk over MSMQ.
We are currently running BizTalk 2010 (with Adapter Pack 2010) and are using ordered delivery for inbound messages to Oracle (received from msmq) but not for outbound messages since the Wcf-adapters doesn't support Ordered Processing in a receive port/location
(except for msmq). However, we do need to implement ordered processing for outbound messages also. It's a major drawback that the Wcf-adapters does not support ordered processing not even with restricted or limited functionality.
Our current implementation is polling Oracle using the Wcf-adapter calling PLSQL-package functions that handles all logic and returns a pre-built XML in a CLOB/string to BizTalk.
Since Oracle is hosted on Linux we can't switch the PLSQL-logic to use Oracle COM-automation and post XML directly into MSMQ which otherwise would have been a quick solution. Also no WebSphere MQ (MQSeries) exists on the premises ruling out that adapter.
Preferences:
- Stable and reliable message transfer with ordered processing from Oracle to BizTalk
- Messaging only pattern (generic) preferred over custom Orchestations (such as re-sequencing pattern)
- Products preferred over custom development (within reasonable price limits).
- Follow Microsoft best practices if possible
In-house development of a custom BizTalk adapter or a nt-service bridging from Oracle to MSMQ could be considered as an option.
regards
/Henrik
/Henrik

Thanks for the reply but it's not that easy I'm afraid, if it had then this post would never have been written.
We're retrieving one message at the time and with pollWhileDataFound=true so that's all good.
The problem is that the inner workings of the wcf-adapters are multithreaded and can not guarantee ordered delivery (which also has proven itself).
The answer why can be found in this post
http://blogs.msdn.com/b/paolos/archive/2009/11/17/customizing-and-extending-the-biztalk-wcf-adapters.aspx
Here's the crucial part: "The WCF Adapters create a separate ServiceHost and singleton service object of this class for each receive location to handle client requests for the lifetime of the BizTalk Host instance running WCF receive locations. The service
object uses multiple threads to process messages concurrently unless the WCF-NetMsmq receive locations are used with the Ordered processing property being selected"
(this is also why I'm wondering why Microsoft doesn't provide the option to run ordered delivery with other wcf-bindings than NetMsmq...)
The search for ordered processing out of Oracle continues...
regards
/Henrik

Are the database tables stored in a sorted order?

Hi-
Are the records in a databse table stored in a sorted order based on key fields??
Thanks.
Ramesh.

A,
Unfortunately, this is not a clearly or fully explained concept in the BC400 class.
As stated in the course text, the ITAB will have the "order" of the DB table.
This may or may not be in actual key order. It depends on whether or not the primary key index is ALWAYS kept up to date / ordered by your DBAs.
This is rarely done as it is very "expensive" to the system... vitually impossible to be truthful.
Because of this, you can never GUARANTEE in a Production system that all records are stored in a primary key order. To guarantee ordering, you must FORCE the system to order the result set through:
ORDER BY
or
SORT after the database retrieval is completed and the result set is returned to the App server

Order of af:resource

I have 2 javascript imports using af:resource in my page. We'll call them a.js and b.js. The b.js has dependencies on the a.js so I declared the af:resource for a.js first then followed by b.js. Oddly enough the actual order of <script> tags in the generated/rendered page is the reverse(e.g. b.js came before a.js). I have tried looking for the official documentation regarding the order af:resource declarations are actually processed but couldn't find any. Is there any guaranteed order for the af:resource?

Hi,
There's no guarantee to my knowledge. You could check the partitioning feature and include your files in the bootstrap one though maybe. You can check http://andyschwartz.wordpress.com/2008/10/14/hello-javascript-library-partitioning/ for an example.
Regards,
~ Simon

DMA RT to FPGA guaranteed order?

Similar Messages

Maybe you are looking for