Does Labview Support a Hierarchical VHDL Instantiation into Labview Clip Nodes?

Question

Hello,
Does Labview Support a Hierarchical VHDL Instantiation into Labview Clip Nodes?
I followed the available help, and called out the top-level VHDL in my XML file.  Unfortunately, my lower level VHDL components are being read as a Black Box and I am getting an error during compile.  So, what must I do to instantiate hierarchical VHDL code into a clip node?
Solved!
Go to Solution.

Answer 1

Yes, but you need to include the paths to all of your VHDL files in your CLIP XML.  This tells LabVIEW which source files to copy into the compilation directory.  Here is an example (which assumes the source files are in the same directory as the XML):
<CLIPDeclaration Name="NI Example CLIP">
  <FormatVersion>1.0</FormatVersion>
  <CLIPVersion>1.0.0</CLIPVersion>
  <HDLName>ExampleClip</HDLName>
  <ImplementationList>
    <Path>ExampleClip.vhd</Path>
    <Path>SubComponent.vhd</Path>
    <Path>Fifo32.ngc</Path>
    <Path>ExampleClip.ucf</Path>
  </ImplementationList>