During synthesis(Xilinx-spartan 6) i am getting below given warnings how can i resolve these warning?

Question

WARNING: unable to clean up previous run data file: N:/verilog program/aps8july2015/p.xst: error renaming "N:/verilog program/aps8july2015/p.xst" to "N:/verilog program/aps8july2015/p.xst.old": permission denied
WARNING: unable to clean up previous run data file: N:/verilog program/aps8july2015/p.syr: error renaming "N:/verilog program/aps8july2015/p.syr" to "N:/verilog program/aps8july2015/p.syr.old": permission denied
WARNING:Xst:3035 - Index value(s) does not match array range for signal <mem_g>, simulation mismatch.
WARNING:Xst:3035 - Index value(s) does not match array range for signal <mem_e>, simulation mismatch.
WARNING:Xst:1336 -  (*) More than 100% of Device resources are used.
along with the warning i am getting some infomation as given below, what does it mean plzz explain me-
Xst:3218 - HDL ADVISOR - The RAM <Mram_mem_g> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
The code in which i am getting problem is-
`timescale 10ns / 1ns
module p (
clk       , // Clock Input
addr     , // address Input
data_t_in , // data input
data_g_in , // data input
data_t_out, // data output
data_g_out, // data output
data_e_in , // Episode input
data_e_out, // Episode output
reset,
cs        , // Chip Select
re
parameter data_WIDTH = 9;
parameter ADDR_WIDTH = 335;
parameter data_t_WIDTH = 12;
parameter data_e_WIDTH = 1;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports-----------------------
input [ADDR_WIDTH:0] addr;
input [data_t_WIDTH:0] data_t_in;
input [data_WIDTH:0] data_g_in;
input [data_e_WIDTH:0] data_e_in;
input  cs;
input re;
input clk;
input reset;
//--------------Output Ports-----------------------
output [data_WIDTH:0] data_g_out;
reg [data_WIDTH:0] data_g_out;
output [data_t_WIDTH:0] data_t_out;
reg [data_t_WIDTH:0] data_t_out;
output [data_e_WIDTH:0] data_e_out;
reg [data_e_WIDTH:0] data_e_out;
//--------------Internal variables----------------
 reg [data_WIDTH:0] mem_g [0:ADDR_WIDTH]; //
reg [data_t_WIDTH:0] mem_t [0:ADDR_WIDTH]; //
reg [data_e_WIDTH:0] mem_e [0:ADDR_WIDTH]; //
integer i;
//--------------Code Starts Here------------------
// Memory Write Block
// Write Operation
always @(posedge clk)
begin
if (reset == 1) begin
    for (i = 0; i < 336 ; i = i + 1) begin
       mem_t[i] <= 2800;
     end
  end
  else if (cs && !re) begin
     mem_g[addr] <= data_g_in;
     mem_t[addr] <= data_t_in;
     mem_e[addr] <= data_e_in;
  end
 else if (cs && re) begin
    data_g_out <= mem_g[addr];
    data_t_out <= mem_t[addr];
    data_e_out <= mem_e[addr];
  end
end
endmodule
 

Answer 1

Hello ,
The Warning "Xst:3218 - HDL ADVISOR" is self explanatory which mentions that your RAM has asynchronous read which is unsupported. 
You can check the following UG at page number 204 for RAM coding guidelines:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/xst_v6s6.pdf
You can also use Block Memory generator core to generate RAM. Check the below doc for more details. 
http://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v7_2/pg058-blk-mem-gen.pdf
check  the Spartan 6 Block Ram user guide:
http://www.xilinx.com/support/documentation/user_guides/ug383.pdf
--Syed
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