Erreur DMA

Bonjour,
j'ai un vi qui marche sans problème et en voulant créer sont executable voici ce que j'obtiens:
Je suis Labview 2010 et Windows7.
merci d'avance

Je viens de trouver la solution: il faut décocher "copier les fichiers de code erreur" dans "avancé" avant de créer l'exécutable.

Similar Messages

Erreur compilation RT

Bonjour,
Après réalisation d'un programme FPGA et de sa compilation dans un CompactRio, j'ai fais le programme RT qui va avec mais au moment de le compiler, il m'affiche l'erreur:
LabVIEW: (Hex 0x627) Le nom de fonction du nœud LabVIEW:FpgaSdkMemoryEmulationWriteAddress:C est introuvable dans la bibliothèque.
Etant donné que je ne saisi pas vraiment a quoi cela est du, je ne peut pas corriger ce probleme...
Est-ce que quelqu'un aurait une idée d'où le probleme pourrait venir ou encore comment le régler ?
Merci d'avance,
Nathan
Résolu !
Accéder à la solution.

Bonjour,
Je pense que vous avez utilisé un élément qui n'est pas compatible sur la partie RT.
Vous devriez utiliser les DMA FIFOs pour transférer vos données de l'hôte vers le FPGA et du FPGA vers l'hôte.
Vous avez un exemple ici :
https://decibel.ni.com/content/docs/DOC-9893
Brice S.
National Instruments France

Conflit DMA sur PC/104-GPIB

Bonjour,
J'ai des problemes a faire fonctionner une carte GPIB PC/104 :
Lors de l'installation de celle-ci, le wizard me retourne une erreur de conflit DMA, mais en verifiant dans le gestionnaire de peripheriques, l'adresse DMA n'est utilisée par aucun autre periph. (d'ailleurs, l'IRQ est unique egalement).
J'essaye malgré tout de communiquer avec un instrument, celui ci est trouvé (quand je clique sur "scan for instruments) mais je n'arrive pas à communiquer avec(l'ecriture echoue).
Si j'essaye de faire fonctionner mon appli VB6, je remarque que la carte recois les comande que je lui envoi mais elle est incapable de me répondre quoi que ce soit.
A noter que j'ai 2 modeles differents de PC au format PC 104, le 1er fonctionne parfaitement, c'est avec le 2eme que j'ai les problemes cités plus haut. Les bios des 2 pcs sont a priori configurés de la meme maniere (tous les parametres equivalents entre les 2 pcs sont à la meme valeur).
J'utilise les pilotes V1.7. J'ai également essayé le pilote V1.6 qui a les memes problemes (à la difference qu'avec la 1.6, la recherche d'instruments ne fonctionne pas)
Auriez-vous une solution à me proposer ou des essais à me faire faire ?
Merci d'avance,
Lionel

Pour ceux que cela intéresse : le message est dupliqué ici (avec réponse).
Merci,
Charlotte F. | CLAD
National Instruments France
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>> "Du 11 octobre au 17 novembre, 2 sessions en parallèle : bien démarrer - approfondir vos connais...

Utilisation du DMA avec le pad 6015

Bonjour,
Lors que j'excute un programme permettant de mesurer la largeur d'implulsion ( voir fichier joint, fichier d'exemple fourni par NI). Labview me renvois le message d'erreur -200141 et me propose d'utiliser le DMA chose que je ne sais pas paramétrer. Merci d'avance pour votre aide.
Renseignements complémentaires :
systéme d'exploitation XP pro
labview version 7.1
systéme d'acquisition pad 6015
Attachments:
Meas Pulse Width-Buffered-Cont.vi ‏64 KB

Bonjour,
Cette erreur vient du fait que le DAQ pad 6015 a une très petite FIFO pour les compteurs et qu'il ne supporte pas les DMA pour les compteurs.
Le petit buffer se remplit très vite et provoque des erreurs. Les solutions possibles sont:
- Utiliser un autre module DAQ (PCI serie E)
- Convertir le signal compteur en analogique et le lire en utilisant l'entrée analogique.
Cordialement
VéroniqueD
NI France

Qu'arrive-t-il si je ne lis pas les données dans un FIFO DMA?

Bonjour,
J'aimerais savoir ce qui arrive lorsque je ne lis pas les données dans un FIFO DMA. Est-ce que lorsque le FIFO DMA est plein, la nouvelle donnée est mise dans la file d'attente en faisant tout simplement sortir la plus ancienne donnée?
Merci

Bonjour,
J'imagine que vous utilisez un CompactRIO ou une carte FPGA.
CE qu'il faut savoir, c'est qu'une FIFO DMA est composée de 2 parties, une partie sur le composant FPGA (de la taille indiquée lors de la création de la FIFO) et une partie sur le Hote (Windows ou RT) beaucoup plus grande, et dont on peut faire varier la taille à l'aide d'un noeud de méthode de la palette FPGA Interface.
Quoiqu'il en soit, lors de l'écriture dans la FIFO, ces 2 buffeurs vont se remplir. Lorsque les 2 seront plein, la fonction d'écriture vous retournera une erreur de Timeout, et la donnée que vous avez essayé d'écrire sera tout simplement perdue.
Cordialement,
Olivier L. | Certified LabVIEW Developer

Analog out DMA performance problems

I'm working on an open-source driver for m-series and e-series boards (http://www.comedi.org). I've discoved some performance problems doing dma to analog outputs that I can't resolve. In summary, dma transfers to the analog output of a PXI-6281 in a pxi crate being controlled through a mxi-4 connection (pxi-pci8336) are VERY slow. I'm talking 250k samples/sec slow. That's the maximum speed the dma controller can fill the board's analog output fifo from host memory. I've also got an older PXI-6713 in the same crate, and dma transfers to it are about 15 times faster (about 3.5M samples/sec). I did notice that clearing the dma burst enable bit in the mite chips channel control register caused the 6713 to slow way down to something comparable to the 6281 (about 500k samples/sec). Setting or clearing the burst enable bit had no effect on the speed of the 6289. Is there some special mojo that needs to be done to enable burst transfers on the 6289? Also, even the relatively speedy 6713 does dma transfers much slower than it should, since the pxi-pci8336 advertises 80MB/sec sustained transfer rates over mxi4. Can you provide any insight into this matter? I've already looked through the ddk, and a register level document describing the mite chip, and example code which had chipobjects for the mite and an analog input example.
By the way, dma transfers for analog input on the 6281 weren't as bad, I didn't measure the transfer time, but I was at least able to do input at 500k samples/sec without fifo overruns.
I'll post more detailed performance measurements in a subsequent post, and include measurements for a couple other similar pci boards (a pci-6289 and pci-6711). In case you're wondering, neither of the pci boards get anywhere close to the bandwidth provided by the pci bus, but they're not as spectacularly bad as the pxi-6281.

Here are my measurements:
PCI-6711, tested on 1.4GHz Pentium 4:
5.2 to 5.3 milliseconds to load fifo to half-full using dma. 0.9 to 1.0 microseconds to write to a 16-bit register. 1.9 to 2.1 microseconds to read from a 16-bit register. The mite's burst enable bit has no effect.
PXI-6713, tested on 3.2GHz Pentium D:
2.2 to 2.4 milliseconds to load fifo to half-full using dma. 0.5 to 0.7 microseconds to write to a 16-bit register. 5 to 7 microseconds to read from a 16-bit register. Turning off the mite's burst enable bit causes the dma fifo load time to increase to 16 to 17 milliseconds.
PCI-6289, tested on 3GHz Pentium 4:
2.0 to 2.2 milliseconds to load fifo to half-full using dma. 0.4 to 0.6 microseconds to write to a 16-bit register. About 1.2 microseconds to read from a 16-bit register. The mite's burst enable bit has no effect. I could do streaming analog output on 1 channel with an update rate of about 2.1MHz before the board's fifo started to underrun.
PXI-6281, tested on 3.2GHz Pentium D:
18 to 19 milliseconds to load fifo to half-full using dma. 0.3 to 0.4 microseconds to write to a 16-bit register. 4 to 6 microseconds to read from a 16-bit register. The mite's burst enable bit has no effect. I could do streaming analog output on 1 channel with an update rate of about 250kHz before the board's fifo started to underrun.
Notes: the 671x boards have a 16k sample ao fifo, the 628x boards have 8k.
The 4 to 7 microseconds times to read a register on the PXI boards seems large too, is that normal overhead for going over the mxi-4 connection?
I wasn't doing anything else intensive on the pci bus during these tests. For what it's worth, according to pci specs the two pci boards should be able to dma their analog output fifos to half full in less than 150 microseconds.

1.2 bios flash works fine on P35 Platinum but still having DMA/PIO trouble on XP

After all the scare stories of the latest bios I thought I should mention that it worked like a charm for me. I went from default 1.0D to 1.2 using the MSI Forum HQ USB flashing tool: https://forum-en.msi.com/index.php?topic=108079.0 not using any windows or floppy util.
Once flashed I switched-off and unpluged it for a few minutes, then when I turned on I pressed the little reset button next to the battery on the motherboard. Then I cycled the power a few times till the monitor came to life and asked me to press F1 to reset the clock and stuff. Works great!
Now the problem I was trying to fix is that I only have IDE drives and although it boots up saying DMA mode 6 when I do something intensive such as launch Quake4 or install SP2 it reverts to PIO mode and renders it unplayable.
Same problem on both XP64 and 2003 32bit. Linux and Vista64 work great but I wanted an OS for games. Anyone else solve this problem?

Quote from: Del UK on 06-June-08, 01:38:01
The controller is set to IDE and not raid???
Go into bios
Integrated Peripherals
On Chip ATA Devices.
PCI IDE Bus Master = Enabled
On Chip Sata Controller = Enable
RAID Mode = IDE
I have not had any issues with drivers under:-
XP Home SP2 & SP3
XP Pro SP3
Suse Linux 10.2 or 10.3 64bit
Unbuntu 7.1 64Bit
Also check your IDE cable, if you have issues with 80 pin, drop to 40 pin connection, there is no speed loss on optical drives.
I am sure the guidance will help you.
ATB
Del
all done.
ide cable is that in the motherboard box
all that options in the bios are like your

Data Transfer b/w Target and host using DMA FIFO's

Dear NI,
Am facing a problem while writing data into the DMA in the Host environment,
Steps i did:
1. Invoked the FIFO in the Host environment.
2.Connected it to the VI reference.
3.Configured the DMA Depth.
4.Started the FIFO.
5.An Array is initialised and adata is fed into Array using the File operations.
6.and the DMA is read in the Target VI.,
In the Above process, i attached a indicator to the DMA while reading in the Target environment,
but i could not observe any activity,
if some one tried please let me know the procedure to do the same,
am attaching the Host VI for reference
Attachments:
host.vi ‏172 KB

Hi Kalyansuman,
Good afternoon and thanks for your post.
I would again like to stress you must keep your post in one place on the forums. Now lets discuss your problem!
I am confused about what your trying to acheive. You want to read and write data from the FPGA?
Then normal setup is to open a FPGA VI reference, then do the read/write and close the reference outside of the loop.
If
then require to do this twice, I would have two loops. (but use the
same references), then merge the error clusters, and the use a single
close FPGA reference.
The reason why your DMA may not be working:
1) Have you tried them on their own (just a read for example)?
2) Have you taken a look at the examples in NI Example finder? They have two which show how to implement FIFOs.
3) Is this a cRIO or an R-series board?
Any more clarifcation would be great. For example,do you get an error? what do you mean by no activity?
Kind Regards
James Hillman
Applications Engineer 2008 to 2009 National Instruments UK & Ireland
Loughborough University UK - 2006 to 2011
Remember Kudos those who help!

Stand alone application(.exe) : Error 7 occurred at Open File+.vi: Open File (error: L'erreur 7 s'est produite à : Open File+.vi:Open File)

Dear group members - as i am trying to build a stand alone application , i ran into this problem : "Error 7 occurred at Open File+.vi: Open File" (L'erreur 7 s'est produite à : Open File+.vipen File)
when i select continue i get this error message: "Error 7 occurred at open/create/replace file in Write spreadsheet string.vi->Write To Spreadsheet File (I64).vi->Mono Com Write ini.vi->mainVI2.vi"" ( "L'erreur 7 s'est produite à : Ouvrir/Créer/Remplacer un fichier dans Write Spreadsheet String.vi->Write To Spreadsheet File (I64).vi->Mono Com Write ini.vi->mainVI2.vi" )
i didn't get what's the problem with this vi, i have no problem running my VIs
Can any one here help me out ?
here is the project :

Neither can I. When I opened your Project, there were no VIs present on the top level. The Build Spec refers to a Mainv12, which I finally found buried in the folder Interface 2, but when I tried to open it, there were multiple missing VIs. I notice you have an Interface 2.llb -- is this the same as the VIs in the Interface 2 folder? If so, try getting rid of the .llb (at least for the purpose of sharing your code in the Forum) and re-post your code. As it stands, when I open your Project, virtually every entry is marked "Warning: has been deleted, etc." The fact that so much is "missing" means that I can't easily see/understand MainV12, hence can't guess where the File Not Found error is arising. Sorry.
Bob Schor

Report toolkit et erreur 41110

Bonjour à tous et toutes,
Je voudrais essayer d'utiliser le module tookitreport, en particulier pour excel.
J'ai un soucis, en retour j'ai le code erreur 41110, en regardant de plus près l'erreur se situe au niveau de mon excel template.
Je ne vois pas trop ce que je dois mettre, dans l'aide sur le site pour ce code erreur il est écrit la chose suivante :
Problem:
When I use the LabVIEW Report Generation Toolkit to write data to a Microsoft Excel worksheet LabVIEW returns error -41110 even though the cell exists in the worksheet. Why does the error occur?
Solution:
The LabVIEW Report Generation Toolkit supports writing data only to the first worksheet in a workbook. To fix the error, make sure you write the data to the first worksheet.
Hors le fichier que j'ai mis, est juste un fichier excel vierge de toute case.
J'ai mis en piece jointe le classeur vierge excel et le fichier labview (le deux vi est pour labview 9.0, au cas ou).
Résolu !
Accéder à la solution.
Pièces jointes :
génération essai.vi ‏15 KB
essai.xls ‏14 KB
génération essai.vi ‏12 KB

Bonjour,
Vous n'avez pas de Worksheet "truc" dans votre document. En rendant ce string vide, vontre programme fonctionne:
Cordialement
Florian Abry
Application Engineer Group Leader
NI Germany

How can i send more than one signal to DMA FIFO?

Hello,
I'm trying to send more than one signal to DMA FIFO, but i don't know how to do. When i send one signal i don't have problems. I try to use one block DMA FIFO for one signal. For example if i have 3 signal i use · DMA FIFO but whe i want to wath them in a waveform chart the signals have a delay.
How can I do to send more than one signal to DMA FIFO? and if that's no posible, How i can do for syncronizate the 3 signals?
The data type of the signal is FXP <16,10>
Regards.
Pablo
Solved!
Go to Solution.
Attachments:
Block Diagram.jpg ‏81 KB
Block Diagram.jpg ‏81 KB

Not quite. You need to use the Integer To Fixed Point Cast to change from the integers to your FXP numbers. You can then build them into a cluster to write to the Waveform Chart.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines
Attachments:
Combine and Decode FXP.png ‏14 KB

How to set a DMA transfer type for PXIe-6536 in LabWindows/CVI?

I have a PXI chassis PXIe-1078 with a controller PXIe-8115 running under Windows 7. The digital output board is PXIe-6536.
I use a function DAQmxSetChanAttribute to set a property DAQmx_DO_DataXferMech to a value DAQmx_Val_DMA, since I want to use a direct memory access data transfer. This wokred well with a PCI-6534 board using the same LabWindows/CVI code before migrating it to the PXIe system.
Unfortunately, running this code on the PXIe system reports a DAQmx error -200452: "Specified property is not supported by the device or is not applicable to the task".
The task is created in the following simple way (the board name in MAX is 'Dev1'):
   DAQmxCreateTask ("digTask", &digitalTask);
   DAQmxCreateDOChan (digitalTask, "Dev1/port0:3", "DIG_CHANNELS", DAQmx_Val_ChanForAllLines);
   DAQmxSetChanAttribute (digitalTask, "", DAQmx_DO_DataXferMech, DAQmx_Val_DMA, 15);
How can I solve this problem? How is it possible to choose between different transfer types?
Thank you in advance for any hint!

Hi CavityQED,
The PCI-6534 is a "Digital I/O" board while the PXIe-6536 is a "High Speed Digital I/O" board, that's why they don't have the same properties.
By the way you can use DMA transfer with this method :
http://zone.ni.com/reference/en-XX/help/370520J-01/hsdio/direct_dma/
Let me know if it helps you.
Regards.
Mathieu_T
Certified LabVIEW Developer
Certified TestStand Developer
National Instruments France
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Using DMA to update values in an array

Good afternoon,
I've been running into a few problems with my vi, and I'd like to give a bit of the background information before I ask my questions. I'm using Labview 8.5 and the NI USB-6009 DAQ. I want to use an encoder to control values that are being written to a file for DMA. I found that I couldn't use the encoder as an external clock since the 6009 DAQ doesn't have this capability. So I've been trying to go a differenet route by using a case structure with a True/false statement to allow me to input values from a simulated signal into a write vi (each time the encoder pulses, a value from the simulated signal should be inputed into the write data storage vi). From there, I want to then read those values and put them into an array. So the plan is to have a 10 element array that reads in values from the storage file (just like in FIFO for FPGA). As I continue reading values, the oldest value of the 10 element array will leave the array and be replaced by a new value.
Now here come the questions, I'm using the Write/Read data storage vi's and I keep getting errors. First, if I'm wanting to use DMA to read these values am I using the correct vi's, or is there a different route? Also, once I read these values into the array how would I be able to constantly update the array in a descending order from begining to end of the stored values?
I'm posting my most recent vi that I've been editing. Also, in advance, thank you!
-tjm
Attachments:
Using Encoder as an analog input 10_9_13 - Copy - Copy.vi ‏390 KB

Thank you for your reply.
First, I'm ultimately trying to use the array as input into a visual display for a meter (to display the mean of the array). I've been successful (in the past) with inputting into an array by not using DMA and using the Sort 1D Array point by point vi. The only problem is the timing mechanism with the encoder, and you are correct with stating that there is uncertainty with the encoder when trying to retrieve values from the input signal (sine wave). I thought about going down the route of using the encoder as a counter (since I am able to see the counter increase by a single digit with each pulse).
My question would then be how to control the case structure with a counter input?
I'm posting both my setup with the Sort 1D Array Point by Point and the simple vi for the encoder as a counter. My idea is to try to merge the two and have the counter control the case structure.
Is there a way I can do this?
Attachments:
Sort 1D Array Pt by Pt.vi ‏189 KB
Using Encoder as a counter input 10_9_13.vi ‏123 KB

NI 5112 DMA Performance

Hi,
I am currently doing continuous data acquisition with the NI 5112 using an sample rate of 2*20 MSamples/s (using fetchBinary8) for software defined radio. I transfer the data from the 5112 into the main memory in real-time and it works fine.
However, this continouos data transfer needs much CPU performance of nearly 100% of one 3 GHz P4 (I have a dual-processor system) and I would need this CPU also to process the data. I don't understand that since DMA transfer should not require CPU cycles. Has anyone an explanaition of that?
thanks, thomas

What is the "chunk size" when you are continuously fetching data? If
you're using LabVIEW and you leave the number of points to fetch as -1
in the read/fetch VI, the VI will return as soon as it finds a non-zero
number of points to fetch. Depending on how fast your computer is and
your sample rate, you may be getting only a few points per iteration in
the loop. Setting the number of points to a larger value, say 1M for
example, may improve your CPU usage. Also, be sure to set a non-zero
timeout value because if the timeout is zero, the available points are
returned regardless of the number of points requested. Also, is this system in PCI or PXI?
The CPU usage may still be higher than you expect because we DMA the
data from the board to a temporar
y buffer before copying it to your
buffer. We do this because we can only transfer a minimum of 256 bytes
at a time with DMA. If an acquisition is less than that size or a
non-multiple of 256 bytes, some of the points at the beginning and end
of the acquisition will be invalid. Since we don't want to make the
user have to think about all that stuff, we return a buffer that is
exactly what was asked for. Unfortunately, that requires an extra copy
of the data. We may add direct DMA to the user buffer in a future
release of NI-SCOPE.
I'd be interested to hear how well your application still runs after you
add your processing algorithms into your program. You may find that the
CPU yields time and it still works ok. If not, check back with us and
we can look at alternative ways to improve the performance.

M-Series Buffered Event Counting with DMA -- gating problem

Hi --
I am implementing DMA-based buffered event counting on a PCIe-6259 board. I use G0_Out as the gate for G1, which counts events on a PFI pin. So by setting the speed of G0, I get an event count (either cumulative or non-cumulative) on a periodic basis, which is directly DMA'd to my buffer, and synchronized with other i/o operations.
This is working well right now, except for one problem, which is that the I only get data if there is at least one source edge between gates. i.e. if there are no edges, nothing gets pumped to the dma buffer.
I am guessing that a stale data error is somehow choking off the DMA transfer from the counter. Is that possible?
Is there some magic that I need to do to avoid this, because for this application, especially if I am counting cumulatively, I don't care about a missing edge, but I do care if the dma transfers get out of phase with the rest of my timing.
Thanks in advance for any help!
--spg
Here is a snippet of the code that sets up the event counting on G1, partly based on gpctex6.cpp:
const int sDMASelect[] = {1,2,4,8,3,5};
// source: pfi, or -1 for 20Khz clock
void eventTimerSetup(tMSeries *board, tTIO *tio, int dmaChannel, bool cumulative, int source)
   int sourceSelect = (source==-1) ? 0 : (source+1);
   //MSeries.CTR.Source
   tio->G1_Input_Select.setG1_Source_Select(sourceSelect); // (pfi+1) or 20Khz=0
   tio->G1_Input_Select.setG1_Source_Polarity(0); //rising=0
   tio->G1_Input_Select.setG1_OR_Gate(0);
   tio->G1_Input_Select.flush();
   //MSeries.CTR.Gate
   tio->G1_Input_Select.setG1_Gate_Select(20); //the G_OUT signal from other clock=20
   tio->G1_Input_Select.setG1_Output_Polarity(0); //active high=0
   tio->G1_Input_Select.flush();
   //MSeries.CTR.IncrementRegisters
   tio->G1_AutoIncrement.writeRegister(0);
   //MSeries.CTR.InitialCountRegisters
   tio->G1_Mode.writeG1_Load_Source_Select(tTIO::tG1_Mode::kG1_Load_Source_SelectLoad_A);
   tio->G1_Load_A.writeRegister(0);
   tio->G1_Command.writeG1_Load(1);
   tio->G1_Load_B.writeRegister(0);
   tio->G1_Load_A.writeRegister(0);
   tio->G1_Command.setG1_Bank_Switch_Enable(tTIO::tG1_Command::kG1_Bank_Switch_EnableBank_X);
   tio->G1_Command.setG1_Bank_Switch_Mode(tTIO::tG1_Command::kG1_Bank_Switch_ModeGate);
   tio->G1_Command.flush();
   //MSeries.CTR.ApplicationRegisters
   tio->G1_Input_Select.setG1_Gate_Select_Load_Source(0);
   tio->G1_Mode.setG1_Reload_Source_Switching(tTIO::tG1_Mode::kG1_Reload_Source_SwitchingAlternate);
   tio->G1_Mode.setG1_Loading_On_Gate(cumulative ? tTIO::tG1_Mode::kG1_Loading_On_GateNo_Reload : tTIO::tG1_Mode::kG1_Loading_On_GateReload_On_Stop_Gate);
   tio->G1_Mode.setG1_Loading_On_TC(tTIO::tG1_Mode::kG1_Loading_On_TCRollover_On_TC);
   tio->G1_Mode.setG1_Gating_Mode (tTIO::tG1_Mode::kG1_Gating_ModeEdge_Gating_Active_High);
   tio->G1_Mode.setG1_Gate_On_Both_Edges (tTIO::tG1_Mode::kG1_Gate_On_Both_EdgesBoth_Edges_Disabled);
   tio->G1_Mode.setG1_Trigger_Mode_For_Edge_Gate(tTIO::tG1_Mode::kG1_Trigger_Mode_For_Edge_GateGate_Does_Not_Stop);
   tio->G1_Mode.setG1_Stop_Mode(tTIO::tG1_Mode::kG1_Stop_ModeStop_On_Gate);
   tio->G1_Mode.setG1_Counting_Once(tTIO::tG1_Mode::kG1_Counting_OnceNo_HW_Disarm);
   tio->G1_Second_Gate.setG1_Second_Gate_Gating_Mode(0);
   tio->G1_Input_Select.flush();
   tio->G1_Mode.flush();
   tio->G1_Second_Gate.flush();
   //MSeries.CTR.UpDown.Registers
   tio->G1_Command.writeG1_Up_Down(tTIO::tG1_Command::kG1_Up_DownSoftware_Up); //kG1_Up_DownSoftware_Down
   //MSeries.CTR.OutputRegisters
   tio->G1_Mode.writeG1_Output_Mode(tTIO::tG1_Mode::kG1_Output_ModePulse);
   tio->G1_Input_Select.writeG1_Output_Polarity(0);
   //MSeries.CTR.BufferEnable
   board->G1_DMA_Config.writeG1_DMA_Reset(1);
   board->G1_DMA_Config.setG1_DMA_Write(0);
   board->G1_DMA_Config.setG1_DMA_Int_Enable(0);
   board->G1_DMA_Config.setG1_DMA_Enable(1);
   board->G1_DMA_Config.flush();
   tio->G1_Counting_Mode.setG1_Encoder_Counting_Mode(0);
   tio->G1_Counting_Mode.setG1_Alternate_Synchronization(0);
   tio->G1_Counting_Mode.flush();
   //MSeries.CTR.EnableOutput
   //board->Analog_Trigger_Etc.setGPFO_1_Output_Enable(tMSeries::tAnalog_Trigger_Etc::kGPFO_1_Output_EnableOutput);
   //board->Analog_Trigger_Etc.setGPFO_1_Output_Select(tMSeries::tAnalog_Trigger_Etc::kGPFO_1_Output_SelectG_OUT);
   //board->Analog_Trigger_Etc.flush();
   //MSeries.CTR.StartTriggerRegisters
   tio->G1_MSeries_Counting_Mode.writeG1_MSeries_HW_Arm_Enable(0);
   board->G0_G1_Select.writeG1_DMA_Select(sDMASelect[dmaChannel]);
   tio->G1_Command.writeG1_Arm(1); // arm it
Scott Gillespie
http://www.appliedbrain.com
scott gillespie
applied brain, inc.
Solved!
Go to Solution.

Okay, I have it working now. In addition to your suggested changes, I had to remove the following line:
tio->G1_MSeries_Counting_Mode.writeG1_MSeries_HW_Arm_Enable(0);
It appears that writing something to MSeries_Counting_Mode causes that register to supersede the Counting_Mode register. Is that right?
So code that now works for me is listed below.
thanks Tom!
-spg
void eventCounterSetup(tMSeries *board, tTIO *tio, int dmaChannel, bool cumulative, int source) // pfi, or -1 for 20Khz clock
int sourceSelect = (source==-1) ? 0 : (source+1);
//MSeries.CTR.Source
tio->G1_Input_Select.setG1_Source_Select(sourceSelect); // (pfi+1) or 20Khz=0
tio->G1_Input_Select.setG1_Source_Polarity(0); //rising=0
tio->G1_Input_Select.setG1_OR_Gate(0);
tio->G1_Input_Select.flush();
//MSeries.CTR.Gate
tio->G1_Input_Select.setG1_Gate_Select(20); //the G_OUT signal from other clock=20
tio->G1_Input_Select.setG1_Output_Polarity(0); //active high=0
tio->G1_Input_Select.flush();
//MSeries.CTR.IncrementRegisters
tio->G1_AutoIncrement.writeRegister(0);
//MSeries.CTR.InitialCountRegisters
tio->G1_Mode.writeG1_Load_Source_Select(tTIO::tG1_Mode::kG1_Load_Source_SelectLoad_A);
tio->G1_Load_A.writeRegister(0);
tio->G1_Command.writeG1_Load(1);
tio->G1_Load_B.writeRegister(0);
tio->G1_Load_A.writeRegister(0);
tio->G1_Command.setG1_Bank_Switch_Enable(tTIO::tG1_Command::kG1_Bank_Switch_EnableBank_X);
tio->G1_Command.setG1_Bank_Switch_Mode(tTIO::tG1_Command::kG1_Bank_Switch_ModeGate);
tio->G1_Command.flush();
//MSeries.CTR.ApplicationRegisters
tio->G1_Input_Select.setG1_Gate_Select_Load_Source(0);
tio->G1_Mode.setG1_Reload_Source_Switching(tTIO::tG1_Mode::kG1_Reload_Source_SwitchingAlternate);
tio->G1_Mode.setG1_Loading_On_Gate(cumulative ? tTIO::tG1_Mode::kG1_Loading_On_GateNo_Reload : tTIO::tG1_Mode::kG1_Loading_On_GateReload_On_Stop_Gate);
tio->G1_Mode.setG1_Loading_On_TC(tTIO::tG1_Mode::kG1_Loading_On_TCRollover_On_TC);
tio->G1_Mode.setG1_Gating_Mode (tTIO::tG1_Mode::kG1_Gating_ModeEdge_Gating_Active_High);
tio->G1_Mode.setG1_Gate_On_Both_Edges (tTIO::tG1_Mode::kG1_Gate_On_Both_EdgesBoth_Edges_Disabled);
tio->G1_Mode.setG1_Trigger_Mode_For_Edge_Gate(tTIO::tG1_Mode::kG1_Trigger_Mode_For_Edge_GateGate_Does_Not_Stop);
tio->G1_Mode.setG1_Stop_Mode(tTIO::tG1_Mode::kG1_Stop_ModeStop_On_Gate);
tio->G1_Mode.setG1_Counting_Once(tTIO::tG1_Mode::kG1_Counting_OnceNo_HW_Disarm);
tio->G1_Second_Gate.setG1_Second_Gate_Gating_Mode(0);
tio->G1_Input_Select.flush();
tio->G1_Mode.flush();
tio->G1_Second_Gate.flush();
//MSeries.CTR.UpDown.Registers
tio->G1_Command.writeG1_Up_Down(tTIO::tG1_Command::kG1_Up_DownSoftware_Up); //kG1_Up_DownSoftware_Down
//MSeries.CTR.OutputRegisters
tio->G1_Mode.writeG1_Output_Mode(tTIO::tG1_Mode::kG1_Output_ModePulse);
tio->G1_Input_Select.writeG1_Output_Polarity(0);
//MSeries.CTR.BufferEnable
board->G1_DMA_Config.writeG1_DMA_Reset(1);
board->G1_DMA_Config.setG1_DMA_Write(0);
board->G1_DMA_Config.setG1_DMA_Int_Enable(0);
board->G1_DMA_Config.setG1_DMA_Enable(1);
board->G1_DMA_Config.flush();
// from Tom:
// The "magic" you need is referred to as synchronous counting mode (or Duplicate Count Prevention in NI-DAQmx).
// Try setting G1_Encoder_Counting_Mode to 6 (synchronous source mode) and G1_Alternate_Synchronization to 1 (enabled).
tio->G1_Counting_Mode.setG1_Encoder_Counting_Mode(6); // 0
tio->G1_Counting_Mode.setG1_Alternate_Synchronization(1); // 0
tio->G1_Counting_Mode.flush();
board->G0_G1_Select.writeG1_DMA_Select(sDMASelect[dmaChannel]);
tio->G1_Command.writeG1_Arm(1); // arm it
scott gillespie
applied brain, inc.

Erreur DMA

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