Error -1074116136 when changing external sampling CLK

Question

I am running a PXI 5105 with an external sampling CLK supplied to the PFI1 by a PXIe 6556. As long as I start up with a fixed frequency, things will run fine. But as soon as I change the 6556's CLK frequency on the fly, I will run into the following error as soon as the next "niScope Multi Fetch Cluster" is executed:
Error -1074116136 occurred at niScope Multi Fetch Cluster.vi:1
Possible reason(s):
Hardware clocking error occurred.
If you are using an external reference or sample clock, make sure it is connected and within the jitter and voltage level specifications at all times. Also, verify that its rate matches the specified clock rate. If you are generating your clock internally, please contact National Instruments Technical Support.
Status Code: -200551
Is there anything I can do to re-sync the 5105 to the new external CLK frequency?
Thanks a lot and best regards,
Georg

Answer 1

Hey Georg,
in case you haven't fixed the problem yet, I figured out a way to change the frequency without altering the initial frequency. I assume you are using LabView to configure your system. I guess you are using a fixed pattern like "10101010" that your Computer writes into the buffer of the card in order to implement CLK action.
Problem is, that your Card will always go through this pattern with the fixed frequency that you've used to initialize the "read" vi with. From my point of view its not possible to re-set this frequency to another value.
But what you can do - in order to solve the problem - change the pattern that you use for the clock. For example:
Let's say right now you use an U8 Integer to implement your clock pattern: What you want is "10101010" = 128+32+8+2=170
so you start the task writing "170" on the data input of your "write vi".
Now you wanna change the frequency -> so just change the pattern to e.g. 10001000=128+8=136
Since you know that your card will sent a CLK impuls for every "1" that is found, you now have a CLK signal that is much slower than the before signal.
I hope this can help in order to work around your problem
Best regards