Error 42201 the input signal is empty

hi all
can you help fixing this error please ?
error 42201 the input signal is empty .( i am having this error while connecting the build array function to the detrend function .
Bill David

Bill David,
I can see several possibilities for an empty array:
1. You initialize the shift register with an empty array, so if nothing ever gets added to the array it will remain empty.
2. Part of the image is cut off. If an empty string is passed (although you may be testing for this in the cut off portion), the array will be empty.
3. If a non-empty strnig is passed but its format or contents does not translate to a non-empty array of strings, the output of the for loop will be an empty array.
Some additional possiblities could produce non-empty arrays with all zeros, NaN, or Infinities, but those would generate different errors.
Try putting indicators on the data string, on the string array, and on the numeric array to see what you are getting.
Lynn

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dsp_com is port
clock : in std_logic;
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led1: out std_logic_vector(3 downto 0) := (others => '1');
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TYPE State_type IS (S0, S1, S8, S9, S10, S11); -- 12 States
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signal s_DSP_ACK : std_logic ;
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signal data_from_dsp2 : std_logic_vector(3 downto 0);
signal data_from_dsp3 : std_logic_vector(3 downto 0);
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clkdsp : process(clock)
variable count : integer range 0 to 2000 :=0;
variable n :std_logic := '0';
begin
if rising_edge(clock) then
count := count + 1;
if(count >= 2000) then
n := not n;
FPGA_CLK <= n ;
count := 0;
end if;
end if;
end process clkdsp;
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begin
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s_dsp_db_input <= dsp_db_input;
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null;
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--first: process(clock,s_Reset)
-- begin
-- if (s_Reset = '0') then
-- PresentState <= S0;
--elsif rising_edge(clock) then
-- PresentState <= PresentState;
-- end if;
-- end process;
first : process(s_Reset, clock)
begin
if (s_Reset = '0') then
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when S0 => if s_DSP_ACK = '1' then PresentState <= S1;
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-------------------------------single read ADC------------------------------------
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when S11 => if s_DSP_ACK = '0' then PresentState <= S0;
else PresentState <= S11; end if;
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end case;
end if;
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--variable DATA &colon; std_logic_vector(12 downto 0);
begin
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FPGA_ACK <= '0';
led1 <= "1000";
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when S9 =>
FPGA_ACK <= '1';
data_from_dsp1(3 downto 0) <= s_dsp_db_input(3 downto 0);
if(data_from_dsp1 = "0101")then
led1 <= "1001";
else
led1 <= "0000";
end if;
wr_en <= '0'; -- input
when S10 =>
FPGA_ACK <= '0';
data_from_dsp2(3 downto 0) <= s_dsp_db_input(3 downto 0);
if(data_from_dsp2 ="0111")then
led1 <= "1010";
else
led1 <= "0000";
end if;
wr_en <= '0'; -- input
when S11 =>
FPGA_ACK <= '1';
data_from_dsp3(3 downto 0) <= s_dsp_db_input(3 downto 0);
if(data_from_dsp3 ="1000")then
led1 <= "1011";
else
led1 <= "0000";
end if;
wr_en <= '0'; -- input
end case;
end process;
end FSM_Moore ;
i have already synchronize the input signals e.g. dsp_ack, and db_input to the FSM. this is the most frequency problem that cause FSM runs misbehavior
Issue:
Issues:
when i debug the c program in DSP board and FPGA, every thing is ok ! FSM can switch to the next state according to the DSP_ACK.
but if i let the program run. i saw the state is alway stuck at S0 in FPGA, but for the DSP side, the code are still running.
anyone has any ideas to this problem?
appreciate for you guys' reply !
regard,
napon

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Error 42201 the input signal is empty

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