ERROR:MapLib:973 - Tri-state buffers are not supported in this architecture.

Question

Hi,
I face a ERROR:MapLib:973 problem with inout port in a pcore component.
I need ton instantiate an inout port at the top level to communicate wih my peripherical.
This inout port is driven by an XPS IP core (pcore).
The .mpd is  :
PORT fdata = "", DIR = INOUT , VEC = [31:0], ENABLE=SINGLE, THREE_STATE = TRUE,TRI_I = fdata_I, TRI_O = fdata_O, TRI_T = fdata_T
PORT fdata_I = "", DIR = I , VEC = [31:0]
PORT fdata_O = "", DIR = O , VEC = [31:0]
PORT fdata_T = "", DIR = O
The .vhd is :
fdata_o : out std_logic_vector(31 downto 0);
fdata_i : in std_logic_vector(31 downto 0);
fdata_t : out std_logic ;
I got ERROR:MapLib:973 - Tri-state buffers are not supported in this architecture messages for each
signals of my fdata PORT, while mapping !
Thanks for you help.

Answer 1

What device are you targeting, and what version of the software are you using?
I target a xc7k325t-fbg676-2.
I use ISE 14.3 form platgen to xst and 14.7 from map to bitgen.
What does your top level HDL (verilog or VHDL) file look like (where the IO must be instantiated)?
It is a .vhd in whitch i wrapp my top XPS core, described by .mhs
The problematic IO port is instantiated into the mb_core.vhd (generated by XPS).
If i open it, i could see that the tool correctly infer the corresponding IOBUF's :
component mapping :
fdata_I => FX3_DQ_I,
fdata_O => FX3_DQ_O,
fdata_T => FX3_DQ_T,
One IOBUF infered:
iobuf_1 : IOBUF
port map (
I => FX3_DQ_O(31),
IO => FX3_DQ(31),
O => FX3_DQ_I(31),
T => FX3_DQ_T
Top level port :
FX3_DQ : inout std_logic_vector(31 downto 0);
THEN FX3_DQ  signal is dirrectly branched in my upper level (top level) vhd file, with the same name.
What do your constraints file look like (where the pin number and names get declared)?
The port is only constrained in .ucf, like that:
NET FX3_DQ[0] LOC = "B24"| IOSTANDARD = LVCMOS33 ;
NET FX3_DQ[31] LOC = "G26"| IOSTANDARD = LVCMOS33 ;#Bank 14