Faster loop rates

Hello. I am looking for help increasing the execution speed of the attached VIs. The equipment is a PXIe-8135 controller running LVRT, PXIe-6368 DAQ, and PXIe-7966R FPGA. I am using a hardware timed, single point data acquisition loop that will eventually implement some sort of feedback control, and I need the highest possible rate (ideally above 100 kHz). Leaving out the FPGA, I was able to run the loop at 200 kHz on the real time PXI target. However, incorporating the calls to the FPGA has cut that down to about 60-70 kHz. (The FPGA is needed because multiple channels will be added and the computation might get more involved than the RT processor can handle quickly.) Here are some specific questions.
1. Data conversion. Now I am reading data from the DAQ as a floating point double, but then I need to convert it to send data to the FPGA. I am not sure if converting to fixed point rather than single is more efficient? Or should I try reading raw I16 data from the DAQ? I believe this creates an array of integers, so it might be slower?
2. Data logging. If I turn on data logging, the rate is drastically reduced. Is using the built-in TDMS logging from the DAQmx pallete not the best option? This usually works better for me than a parallel data logging loop with local variables.
3. FPGA polling. Would another method be better? For single point transfers, I didn't think DMA FIFOs are the right approach.  I did try the IRQ interrupt method, and it was slightly slower.
I really appreciate any suggestions. Any little tweak will help at this point. Thanks for your help!
Jeff
Attachments:
fpgaVI.png ‏11 KB
targetVI.png ‏25 KB

You are going the expensive route!  Are you using any of the IO on that FlexRIO board?  If not, you are totally going in the wrong direction with this.
Why not just go with something like the PXI-7854R, which can handle your analog inputs and outputs.  And it is cheaper than that DAQ card.  Then all of your acquisition and control logic can happen on the FPGA.  You just have to use a DMA to send the data to the RT system for logging.
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    FPGA Loop Rate 2.PNG ‏5 KB

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  • Loop rate long

    Hi,
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