Ni7842 FPGA RIO board loop rate

Hi,
Is it possible to achieve a loop rate of 1us with the Ni7842 RIO board. It has an onboard clock of 40MHz. I have tried the following approaches to achieve a 1us loop rate and generate a single pulse of 1us duration, but wasn't successful.
1st approach: The above flat sequence was originally with 2 frames, I removed the second processing frame to reduce any possible processing delays and changed counter units to usec with a count of 1. This did not work, minimum pulse width I could generate was 1ms.
2nd approach: I changed counter units to ticks with a count of 40. This also was able to generate a min pulse width of 1ms only.
The AO channel is capable of 1MS/s update rate and with an onboard clock of 40Mhz you would think you can achieve 1us. Why is it being so difficult for me? Please help.
Thanks,
PG

Show some actual code. If possible, supply a stripped down project that shows this issue. I recommend zipping up this project and any needed VIs and posting the zip file.
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[FPGA] Loop rate very slow: Do FPGA I/O nodes in parallel loops block each other?

Hi,
I am using cRIO-9075. Mod1 is NI 9263, Mod2 is NI 9227, Mod3 is 9215.
Please see my VI attached or the given screenshot.
The FPGA code is based on the "NI CompactRIO Waveform Reference Library" (it's the lower loop).
The upper loop was added by me and is writing a waveform from blockmemory to the NI 9263 module (Mod 1).
The data sampled in the lower loop is running at 1 kHz. The control "AO Update Period" for the upper loop has a value of (for example) 10 (=uS).
The problem is, that this loop is running much much slower than it should. Once I disable the FPGA I/O node in the lower loop (as done in the attachments), it's running as fast as it should.
It seems to me, that the FPGA I/O nodes are blocking each other. I tried to figure it out by reading through serveral NI documents, but until now I have no idea how to solve that.
Can you give me some advices? Some general tipps about the VI?
Thanks!
Attachments:
FPGA Loop Rate.PNG ‏72 KB
FPGA Main.vi ‏251 KB

Hi, thanks so far.
Originally the control was inside the loop. Then I tried if it makes a difference if it's outside.
Ok, i really seems to be that default value of "100000" for "AO Update Period".
Starting the VI directly woks like expected. Having "AO Update period" inside the loop makes it possible to control it as it's running.
But, please see the attachment. When starting the FPGA through RT and setting the appropiate value, it does not seem to work. The oscilloscope show's the same behavior like "AO Update Period" was 100000.
But when reading the value of "AO Update Period" afterwards (while the FPGA is running), it shows the expected value of "10".
Having changed the default value to 10 works so far, but I am not able to changed it (see attachment).
So the problem is: Why is "Read/Write control" not working here? Why is still the default value used?
Attachments:
FPGA Loop Rate 2.PNG ‏5 KB

FPGA - Synchronization between two loops with different loop rates.

Hi all,
I am trying to implement an Analog and Quadrature Decoder. Simply put, I have two loops: LOOP 1 with an Analog Input (AI) which is a slower loop rate. Another loop: LOOP 2 has a digital input (input) and counts the Quadrature counts. I understand that Analog conversion is slower, and as a result, LOOP 1 will have a slower higher tick rate. I want to pass the "counts" from LOOP 2 into LOOP1, so that I can synchronize the Analog Input with the number of quadrature counts. My issue at hand is: since LOOP 2 updates at a higher rate. Will the "counts" value that I pass/tunnel from LOOP 2 to LOOP 1 refresh at the LOOP 2's rate or at LOOP 1's rate.
Thanks,
Herrick Chang

hlchang wrote:
Hi all,
I am trying to implement an Analog and Quadrature Decoder. Simply put, I have two loops: LOOP 1 with an Analog Input (AI) which is a slower loop rate. Another loop: LOOP 2 has a digital input (input) and counts the Quadrature counts. I understand that Analog conversion is slower, and as a result, LOOP 1 will have a slower higher tick rate. I want to pass the "counts" from LOOP 2 into LOOP1, so that I can synchronize the Analog Input with the number of quadrature counts. My issue at hand is: since LOOP 2 updates at a higher rate. Will the "counts" value that I pass/tunnel from LOOP 2 to LOOP 1 refresh at the LOOP 2's rate or at LOOP 1's rate.
Thanks,
Herrick Chang
The only way to pass values between two parallel loops is by some sort of global variable (global or locals are fine, as are shared variables although I wouldn't recommend that for FPGA if you don't want to go outside of the FPGA target at all). Don't tunnel anything between two independant loops as they won't be independant anymore.
The local variable will be updated at the rate the writing loop updates it, though your slower read loop will obviously not see every value. Note that the FPGA compiler will protect the local variable access in both loops in order to avoid race conditions. This protection is necessary but expensive in terms of runtime performance of each loop as well as FPGA gate usage.
Rolf Kalbermatter
Rolf Kalbermatter
CIT Engineering Netherlands
a division of Test & Measurement Solutions

Using FPGA and Labview without RIO board.

Dear Sir
I am a student. I want to connect my own FPGA and make a program on labview and then transfer to FPGA.I do not want to buy RIO.Is it possible to work
like that without purchasing RIO.
Thanks a Regards

Hooovahh wrote:
Yes NI supports programming FPGAs using LabVIEW without RIO boards I've been doing it for years and it works great. Here are a few non-RIO products I've used LabVIEW FPGA with.
PCI-E Version
PXI Version
USB Version
The PCIe and PXI cards you mentioned are specifically RIO.
But you managed to program a USB-6225 with LV FPGA? I'm not even sure there is an FPGA on there to program. It is an M series DAQ board.
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Optimum servo pid loop rate

Hi,
I want some confirmation on the optimum pid loop rate and the fastest servo motor operation that we can acheive with Pxi-7352 running on Window.
The manual of 7352 says "62 μs PID loop update rate for up to 2 axes". The requirment is to acheive periodic equi sized straight line and rotary motion ( using yaskawa servo motors in torque mode and 7352 to close position loop ) Both motion are independant and not operating simultaneous i.e rotary completes one full rotation in small steps and then linear moves by one small step then rotary completes next rotation in small steps and again linear motor moves this continues till end of test.
you can observe here that both rotary and liner motion are periodic and move equi spaced distance for each step with small stoppage/dwell time of 500 u sec , The catch is in addition to positional accuracy in terms of 50 -100 microns the time for complete each step is also very crucial and very small (many peridoc steps together consitute complete linear and rotary motion). Find expected velocity profile attached for more details on desired timing.
As the motors have simple and periodic straight line and rotary motion i suppose buffered contour moves are not needed which have limitation of 10 msec between two points, then can the time to acheive each step be as low as 2.5 to 5 msec considering best loop rate of 62.5 u sec and highest/worst pid loop rate of 500 usec.
1. Is the expected timing of 2.5 - 5 m sec feasible assuming that the motor is capable of reaching 5000 rpm which is well above desired speed.
2. 735x series being high performance motion controller what is the order of closed loop timing that we can expect for simple and periodic moves (say in order of 1000 usec or 10 msec)
3. Can i interface one stepper motor and another servo motor where both the motors and drives are in position mode on single 7352 and UMI 7772.
4. Are there any limitation if NI motion is not used for code development and NI motion Assistant along with LabVIEW is used instead.
This is precision application and the component is very small ,the weight of the component would be less than 400 grams so i hope we do not have to consider inertial affect on motion significantly.
Appriciate if some one with similar experience can provide more details.
Regards,
Bipin
Solved!
Go to Solution.
Attachments:
Velocity Profile.png ‏21 KB

Hi Bipin,
thank you for your comprehensive post. I had a close look at your timing specs and I strongly doubt, that these specs can be met with a 7352 board. Even though the PID loop rate of 62.5µs might be enough, both trajectory generator and the supervisory control (host communication, move command sequencing,...) are too slow to meet your requirements. Please note, that the trajectory generator always works with a timing interval of 10 ms, regardless of the operation mode (linear move, contouring, blending,...), so there is no way to reach your timing specs with this product. In general contouring is the fastest way to run a quick succession of moves, as it doesn't require host communication (by the way: onboard programs don't execute much faster, than programs that are running on the host).
I don't want to make negative mareketing for our 735x boards, but your timing requirements are just way beyond the requirements of typical motion control applications and it's probably quite hard to find any COTS product in the market, that can meet these specs.
With this said, I would like to offer you an alternative solution, that is based on NI's FPGA technology. Additionally to a faster trajectory generator a faster control loop is probably also very desireable for your application. Even with the lowest price Virtex-II based R-Series multifunction board (PCI-7830R) you can run PID loops with 5µs cycle time and the trajectory generator at the same rate. You even can use a different type of control algorithm if required. This technology is leveraged very successfull in a lot of applications with very high performance and accuracy requirements (here are some examples).
So these are the pros, but where are the cons? Well, the R-Series boards are general purpose FPGA boards and not ready to run motion control boards, so you need to develop the low-level control application by yourself. The good news here is, that it can all be done graphically in LabVIEW and that there are many ready to run examples for motion control, that can be used as a base for your development. Additionally you may want to have a look at the NI SoftMotion Development Module for LabVIEW, that simplifies the development of motion control applications, but it is not a mandatory tool and the benefits of this module might not be as high for your application, as ithey are for more standard motion control applications.
I hope that helps.
Kind regards,
Jochen Klier
National Instruments

PID loop rate with counters

I'm trying to use a PXI-8106 RT and LabviewRT 8.5 as a PID controller to control 3 motors. I'm measuring the speed of the motors by measuring the frequency of the encoder with a 6608.
This article http://zone.ni.com/devzone/cda/tut/p/id/5423 claims a speed up to 107.5 khz. I've set ethernet to polling and usb off, I didn't turn off the CPU display, but I'll try that as soon as I can. However, I'm not anywhere close to 107khz, best I can get is about 10khz with one channel and about 2 khz with 3 channels. I realize the tests were done with analog inputs, but I was hoping that I'd get at least somewhere close using counters. With the 2Khz rate I really can't do what I need to do.
Does anyone know what a realistic rate would be with this setup?
I'm new at Labview so I may be doing something wrong, although I can't see what it could be. I've done quite a bit of research on the forums before I started to learn from other's examples.
Here's a couple of things I've learned trying to optimize my loops.
Seems like Daqmx has some issues with applying a scale. I have 2 scales, one is just a scale factor, 0.166, the other is .0002. When applying the .0002 factor in Daqmx my performance takes a huge hit, something like 10%! If I just leave it at hz, and do the scaling myself I see no performance penalty.
There is something strange about the timed loop % display in RT8.5, I wrote my own routine using expected end, actual end time, and the period to give me a % loop useage and it matches very well to the RT8.5 display for most of the time, however, when the loop starts missing iterations because I've gone over 100% the RT display drops down to about 50% which pretty much makes it useless.
I've attached a couple of shots of my test loop. I can get this one to almost hit 10 khz. the other screen shots are of how I set up the counter, and how I read the counter. the read counter has the error trap to restart itself. Also I set it to use DMA explicitly somewhere else in the program.
Thanks for any help.
Henri
Attachments:
Main Loop.JPG ‏55 KB
Setup Counter.JPG ‏72 KB
Read Counter.JPG ‏67 KB

Devin,
Thanks for the suggestions.
A couple of related questions for you.
The 200 uSec is leftover from my attempts at getting the 3 PID loops to work within the loop availability. I can run about 70 uSec i.e about 14khz with only a single counter.
I've tried changing the buffers value and it has barely any effect on the speed of the loop. Right now I have 3 counters running with 200uSec timing and I get about 69% loop utilization. With a few missed iterations every once in a while. This is using 10000 samples, if I drop down to 100 samples utilization actually goes up to 70%!? Doesn't make sense to me either, but this is using both my VI and the on screen Timed Structures % of LV8.5RT so I'm trusting it as real,
In theory if I can get my loop rate up to 10 khz I'll only need 10 for the buffers since my top frequency to be measured is 100 kHz.
Funny thing on the RT fifo variable... I turned on FIFO and it actually decreased performance by about 1%, both Total load and Time structures went up... so I turned it off for stop-RT, and got a 3% improvement! Down to 66% time structures.
You mentioned the hardware timing to get a hardware timed single point. Unless I misunderstood the counters, this isn't possible since the sample rate is implicit in the frequency measured? i.e. it latches the count every rising edge.. so I'm my case I'd get a 100 khz sample rate (although obviouslyl that would be the max) Can you let me know if I've missed something there.
I bought this system explicitly based on its dual core and its high speed so I could close my PID loops quickly enough with one CPU and still have processing time left over to log data, etc. And the 6608 card is there so I can get high accuracy for my frequency measurements. However, I'm really struggling to get this thing going.
Any help would be greatly appreciated.
Thanks
Henri

How do you on board loop the memory using pci 6534 implementing LabVIEW. Which VI do you use?

How do you on board loop the memory using pci 6534 implementing LabVIEW. Which VI do you use?

Hello,
You will need to set the Pattern Generation Loop Enable attribute to ON in the DIO Parameter VI. This is
specified on page 2-22 of the 653x User Manual (Jan 2001)
Hope this helps,
LA

Spartan-6 FPGA Dev Board plays Doom, a first-person shooter video game from 1993

Yesterday, I mentioned a port of Professor Nicklaus Wirth’s Oberon programming language and operating system to Saanlima's Pipistrello, a Spartan-6 FPGA development board. (See “Oberon System Implemented on a Low-Cost FPGA Board.”) There are many uses for a dev board however and one of the other ports to this board is the first-person shooter called “Doom,” which was originally developed to run on DOS PCs by id Software.
This FPGA-based implementation uses a recompilation of a source port called “Chocolate Doom” that runs on a 100MHz Xilinx MicroBlaze soft processor instantiated in the Pipistrello board’s Spartan-6 LX45 FPGA with additional HDL to handle the mouse, game controllers, video, and sound. Now running recompiled code for an x86 microprocessor on an FPGA-based, soft-core processor might not be the most obvious way to fully employ a Spartan-6 FPGA, but I think it’s a pretty cool demo nevertheless.
Here’s a short, 26-second video showing DOOM running in demo mode on the Spartan-6 LX45 FPGA:
Note: There are no sound effects in this short video because we didn’t hook up any speakers to the Pipistrello board.

Excellent!
Gotta try Pac-Man. It is so much like the arcade version from the 80's it's scary. Also, Magnus has the Pipistrello working so well you can re-flash to/from Oberon to Pac-Man (or whatever) almost instantly. I mean, flash and boot in under 2 seconds. Quite impressive.

PCI-7041 pid loop rate

Hello,
I have PCI-7041/6040 card with which I would like to perform single point PID control. I have looked at the DAQmx example PID control - single channel.vi to do this. The only thing I am unsure on how to do, is set the loop rate to a specific kHz value. Is this done by using the 'Input Rate' control and how could I verify that the loop is running deterministically and to the rate I have set?
thanks,
David

Hi David
You are correct that the "Input Rate" control will set the loop rate for the example that you are using. There are a few ways to determine if the loop is running deterministically.
One thing you can do is use the "DAQmx is Read or Write Late" VI. If the "is late?" output goes true, your loop is not keeping up with the specified hardware timed acquisition and generation.
Another recommended method to determine if your loop is running determinisitically is to benchmark it using the TimeStamp VI's.
There is a great example in the LabVIEW Example Finder that you can use for this. From the Example Finder, go to
Tookits and Modules >> Real-Time >> Timing >> NI Timestamp Code Timer.
You can combine your PID example code with this example to determine how long it takes for your PID code to execute when running on the real-time target. Just place the code you wish to benchmark in sequence 0 of the sequence structure of the Timestamp Code Timer example VI. This VI will give you some great information including average execution time and maximum jitter.

PWM through NI RIO board

I have Labview Embedded Platform kit ( NI-RIO) board and want to generate pwm through a joystick, which is connected to my PC.
Through this PWM I have to control a servo motor.
Is this possible with NI evaluation kit that I have? Can I just connect a servo motor with a driver, to any of output port of RIO board?
help needed

Hi NapDynamite,
If your servo has a driver, you can connect the driver to any digital I/O of the kit, you will have 4 I/O available, and you can program the logic that your driver need in the board.
Regards,
steve.bm
AE | NI

Need to slow down POLL loop rate

I find that when I configure a device for polling and a connection is opened, the poll rate appears to run as fast as the computer will allow. I need to control the poll loop rate or "scan rate" so it scans once every 100ms. Some devices cannot handle a fast scan rate, must be slower than 10ms. How do I change my scan rate?

Hello,
Thanks for contacting National Instruments.
I think you can accomplish what you are trying to do by using a different mode instead of Automatic. For example, if you use the Scanned mode, then you should be able to set the ExpPacketRate to the value you are interested in using as the poll rate. This information is documented on page 2-59 of the following manual.
http://digital.ni.com/manuals.nsf/webAdvsearch/659F311DE89061978625680F0059DCF7?OpenDocument&vid=niwc&node=132100_US
Hope this helps!
Regards,
Steven B.
Applications Engineering
National Instruments

Maximum loop rate achievable in FP 2010

Hi..
I am developing and application with FP-2010 RT controller. Right now I am in design stag and wondering what will be the maximum loop rate achivable with this controller.
searched ni.com... but didnt get any clue..
I hope some of you would have experienced with this controller.
Any help towards this will be greatly appreciated.
MIRASH

Hi Mirash,
just now I try also to improve the performance of a control loop with the FP-2010.
Up to now I find a limit of 100 msec to transfer one item.
My next trial will be to combine some items to one transfer.
Additionally I ask the question NI but have still no answer.
skyh

FPGA - RIO Evaluation Board - Using the LCD Display

I have the NI LabVIEW RIO Evaluation Board and am trying to find information on using the LCD display. Does anyone know of any documentation/app notes? Thanks in advance.

Thanks for the suggestions ramses64.
I failed to mention that I didn't install the software that came with the evaluation kit. The reason being, I already have LabVIEW and all the modules installed. I was not about to overwrite my perfectly good installation even if the instructions on the box tell me it is perfectly safe to do so.
If there are examples with the kit, then they are buried in an installer/cab file and not directly accessible by simply looking at the CD/DVD contents. I should install the evaluation software onto a virtual machine and see what is revealed.
I'll take a look at the LCD Module this evening and see if it provides any clues.
Thanks!

Out of Memory Error, Buffer Sizes, and Loop Rates on RT and FPGA

I'm attempting to use an FPGA to collect data and then transfer that data to a RT system via a FIFO DMA, and then stream it from my RT systeam over to my host PC. I have the basics working, but I'm having two problems...
The first is more of a nuisance. I keep receiving an Out of Memory error. This is a more recent development, but unfortunately I haven't been able to track down what is causing it and it seems to be independent of my FIFO sizes. While not my main concern, if someone was able to figure out why I would really appreciate it.
Second, I'm struggling with overflows. My FPGA is running on a 100 MHz clock and my RT system simply cannot seem to keep up. I'm really only looking at recording 4 seconds of data, but it seems that no matter what I do I can't escape the problem without making my FIFO size huge and running out of memory (this was before I always got the Out of Memory error). Is there some kind of tip or trick I'm missing? I know I can set my FPGA to a slower clock but the clock speed is an important aspect of my application.
I've attached a simplified version of my code that contains both problems. Thanks in advance for taking a look and helping me out, I appreciate any feedback!

David-A wrote:
The 7965 can't stream to a host controller faster than 800MB/s. If you need 1.6GB/s of streaming you'll need to get a 797x FPGA module.
I believe the application calls for 1.6 GB over 4s, so 400 MB/s, which should be within the capabilities of the 7965.
I was going to say something similar about streaming over ethernet. I agree that it's going to be necessary to find a way to buffer most if not all of the data between the RT Target and the FPGA Target. There may be some benefit to starting to send data over the network, but the buffer on the host is still going to need to be quite large. Making use of the BRAMS and RAM on the 7965 is an interesting possibility.
As a more out there idea, what about replacing the disk in your 8133 with an SSD? I'm not entirely sure what kind of SATA connection is in the 8133, and you'd have to experiment to be sure, but I think 400 MB/s or close to that should be quite possible. You could write all the data to disk and then send it over the network from disk once the aquisiton is complete. http://digital.ni.com/public.nsf/allkb/F3090563C2FC9DC686256CCD007451A8 has some information on using SSDs with PXI Controllers.
Sebastian

Faster loop rates

Hello. I am looking for help increasing the execution speed of the attached VIs. The equipment is a PXIe-8135 controller running LVRT, PXIe-6368 DAQ, and PXIe-7966R FPGA. I am using a hardware timed, single point data acquisition loop that will eventually implement some sort of feedback control, and I need the highest possible rate (ideally above 100 kHz). Leaving out the FPGA, I was able to run the loop at 200 kHz on the real time PXI target. However, incorporating the calls to the FPGA has cut that down to about 60-70 kHz. (The FPGA is needed because multiple channels will be added and the computation might get more involved than the RT processor can handle quickly.) Here are some specific questions.
1. Data conversion. Now I am reading data from the DAQ as a floating point double, but then I need to convert it to send data to the FPGA. I am not sure if converting to fixed point rather than single is more efficient? Or should I try reading raw I16 data from the DAQ? I believe this creates an array of integers, so it might be slower?
2. Data logging. If I turn on data logging, the rate is drastically reduced. Is using the built-in TDMS logging from the DAQmx pallete not the best option? This usually works better for me than a parallel data logging loop with local variables.
3. FPGA polling. Would another method be better? For single point transfers, I didn't think DMA FIFOs are the right approach. I did try the IRQ interrupt method, and it was slightly slower.
I really appreciate any suggestions. Any little tweak will help at this point. Thanks for your help!
Jeff
Attachments:
fpgaVI.png ‏11 KB
targetVI.png ‏25 KB

You are going the expensive route! Are you using any of the IO on that FlexRIO board? If not, you are totally going in the wrong direction with this.
Why not just go with something like the PXI-7854R, which can handle your analog inputs and outputs. And it is cheaper than that DAQ card. Then all of your acquisition and control logic can happen on the FPGA. You just have to use a DMA to send the data to the RT system for logging.
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Ni7842 FPGA RIO board loop rate

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