FPGA - Synchroniz​ation between two loops with different loop rates.

Question

Hi all,
I am trying to implement an Analog and Quadrature Decoder. Simply put, I have two loops:  LOOP 1 with an Analog Input (AI) which is a slower loop rate. Another loop: LOOP 2 has a digital input (input) and counts the Quadrature counts. I understand that Analog conversion is slower, and as a result,  LOOP 1 will have a slower higher tick rate. I want to pass the "counts" from LOOP 2 into LOOP1, so that I can synchronize the Analog Input with the number of quadrature counts. My issue at hand is: since LOOP 2 updates at a higher rate. Will the "counts" value that I pass/tunnel from LOOP 2 to LOOP 1 refresh at the LOOP 2's rate or at LOOP 1's rate.
Thanks,
Herrick Chang

Answer 1

hlchang wrote:
Hi all,
I am trying to implement an Analog and Quadrature Decoder. Simply put, I have two loops:  LOOP 1 with an Analog Input (AI) which is a slower loop rate. Another loop: LOOP 2 has a digital input (input) and counts the Quadrature counts. I understand that Analog conversion is slower, and as a result,  LOOP 1 will have a slower higher tick rate. I want to pass the "counts" from LOOP 2 into LOOP1, so that I can synchronize the Analog Input with the number of quadrature counts. My issue at hand is: since LOOP 2 updates at a higher rate. Will the "counts" value that I pass/tunnel from LOOP 2 to LOOP 1 refresh at the LOOP 2's rate or at LOOP 1's rate.
Thanks,
Herrick Chang
The only way to pass values between two parallel loops is by some sort of global variable (global or locals are fine, as are shared variables although I wouldn't recommend that for FPGA if you don't want to go outside of the FPGA target at all). Don't tunnel anything between two independant loops as they won't be independant anymore.
The local variable will be updated at the rate the writing loop updates it, though your slower read loop will obviously not see every value. Note that the FPGA compiler will protect the local variable access in both loops in order to avoid race conditions. This protection is necessary but expensive in terms of runtime performance of each loop as well as FPGA gate usage.
Rolf Kalbermatter
Rolf Kalbermatter
CIT Engineering Netherlands
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