FPGA code stops when RT code stops

I have developed some FPGA code to manage a piece of hardware. It's setup to read some default front-panel control configuration values and then sit there endlessly responding to signal inputs and producing signal outputs. The FPGA bitfile is written to flash memory so the FPGA loads and starts running almost immediately. So far all is good.
Next I layered onto the system (cRIO-9075) some RT code which opens an FPGA reference to the FPGA front panel and allows me to monitor a few indicators and change the configuration settings and cause the changed configuration settings to be used by the FPGA. So far this seems to work too when I run the RT code interactively (eventually there will be an interface to a host system).
The problem occurs when the RT code is commanded to stop. Stopping the RT code also causes the FPGA code to stop and I don't want the FPGA code to stop. The RT code does not make any calls to command that the FPGA code abort execution. When the RT code is stopped, the only thing it does with regard to the link to the FPGA is to close the FPGA VI reference that was opened when the RT code was started.
What do I need to be doing to cause the FPGA code to continue to run as the RT code is started and stopped?
Solved!
Go to Solution.

I'll have to wait until I get back to the office tomorrow to test this but I think this link has the answer to my problem.
http://lavag.org/topic/16412-confusion-regarding-fpga-deployment/#entry100294
It says: "the Close FPGA reference VI. If you right click you have an option to close or by default close and reset. This means the FPGA VI is reset (read aborted in standard LV speak) when we close the reference."

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What happens to FPGA code when a module it expects is missing?

Hi Folks,
I want to know what happens if you have FPGA code that expects a module to be present running on a system where the module is missing.
We have a RT control system that runs on a cRIO 9014 with a 9111 backplane. There are only two modules in the slots and one of these is the Prosoft Profibus module. The biggest chunk of the FPGA code is taken up with configuring and sending and receiving using this module. Specifically the communications with the module are done by the Read (Memory) and Write (Memory) structures.
We are developing code to use the Ethernet/IP libraries instead of Profibus in some cases. This means the communications moves from the FPGA to the RT. We are considering have the ability to switch be an option.
My concern is that if the FPGA has code in that references the Profibus module, then it might behave badly if the module is not present.
And so my question is if FPGA code tries to reference a module that is not present, what happens? Is it just an error? Will there be no error? What?
Thanks!

I am not familiar with profibus, but why not just remove the module and run it and see what happens? I'm guessing you will get an error, althougth which error I am not sure.
CLA, LabVIEW Versions 2010-2013

Need to compile FPGA code after SVN checkout , why ?

Hi,
Our project uses a FPGA. Lets say, we compile the FPGA code on computer A. The code is working fine, so we upload the code to a SVN server where the whole project folder (including the FPGA Bitfiles folder) is stored in the repository. Now lets say we delete the project folder from computer A. Then, we checkout the project folder from SVN onto computer A. Now if we open the project, VIs that use FPGA code have broken links. The error says that FPGA code is not compiled. I dont seem to understand what is going on and why a perfectly working code stopped working. The same problem also occurs if we checkout the project folder onto say computer B.
What I have noticed is that after we checkout from SVN, the dates and times on all the files is changed to the current date and time. Is there something that depends on date and time of the files when it comes to FPGA compilations ? It is very frustrating, because the compilation takes more than 4 hours.
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Hi,
The compiled code is stored in a seperate file in a FPGA Bitfiles folder. The folder is part of the 'Acquisition' folder and is thus a part of the SVN repository. I think the reference to the compiled code by VIs that use that code must be using an identifying mechanism that is tied to the physical location of this file and not just the name. And I have no idea how to fix this, it just seems wasteful to recompile the FPGA code everytime the project folder is installed on a different computer or even if the folder is reloaded onto the same computer.
Saumil

Fpga code generation error after updating from 8.5.0 to 8.5.1

Hi All,
I have a FPGA-VI which was compiled in LV 8.5.0 without errors. After I updated to 8.5.1 the Code Generation stops, telling me the clock domain is not supported for write FPGA I/O node (see attachment). Also I attached a picture of a simplified FPGA-VI which brings up the same error.
I use a PXI-7833R connected to a cRIO-9151 R Series Expansion Chassis with a NI-9421 modul (8-ch DI, 24V) installed in it.
My original FPGA-Code has a theoretical maximum of 22MHz, so I can't change the clock domain to 40MHz.
Do you have any suggestion how to get the VI compiled?
Uli
Solved!
Go to Solution.
Attachments:
ErrorMessage1.jpg ‏30 KB
FPGA-VI1.jpg ‏17 KB

Hi Ruhmann, hi Basset Hound,
thank you for your reply and giving me a better insight in things.
I started my VI with 40MHz clock domain. The Vi got bigger, some more logic here and some more code there. Finaly the compiler couldn't satisfy the timing any more. Instead of optimising the code, I reduced the clock domain.
Until your post I didn't realise I use CompactRIO I/O. Is There a difference to (let me call it) "direct R-Series I/O"?
I need the Expansion Chassis (Connector 1), the 9421 (8-ch DI) and 94?? (8-ch DO) to connect 24V logic to the FPGA. Additionally I have two SCB-68 (Connector 2+3) for 5V logic (DI, DO, A/B linear position measurement, pulse generation) and some analog input. All code in 1 VI, but distributed in 3 loops.
To change the clock domain back to 40MHz, I have to optimise my code . Well, the code is sloppy , so optimising is OK .
To tell the hole story:
After updating to 8.5.1, my first contact to NI was by phone. The engineer asked for the Code, the project and the hardware.
It took a while for me to put the information in an email. Meanwhile engineer the found a paper with the solution I
mentioned in my second post and send it to me, before looking at my code. The paper said someting about "tightend timing constraints",
"safe communication" and "multiple DMA target to host transfer". Not exactly what I was doing, but I reinstalled
RIO 2.3.1 and ... compile successful.
@ Basset:
The simple VI (picture) in my first post reproducese the issue exactly.
I'm not at work any more, so I can't provide the full code or the SRQ# until tuesday (holiday on monday ).
FYI I'm located in Germany, so I called the german NI support.
Uli

NI9203 - Need to know how to set up the FPGA code for multiple NI9203 modules and how to calibrate the data

Hi. I'm using the NI9203 module to detect pressure, temerature and flow rate of water in a cooling system. I have 17 different inputs coming in therefore i'm using 3 NI9203 modules. I've used the example provided with labview as a base for designing my code. The example can be found here : Program Files\National Instruments\LabVIEW 8.0\examples\CompactRIO\Module Specific\NI 9203.
I've had no problems when testing this code out for a single NI9203 module but when i add code for 3 modules the code will not compile as my resources are over mapped. Is there a simpler way to program the FPGA code.
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Hi havok,
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http://digital.ni.com/public.nsf/allkb/311C18E2D635FA338625714700664816?OpenDocument
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http://digital.ni.com/public.nsf/allkb/E86D8D460C4C092F8625752F00050A61?OpenDocument

FPGA Code Generation fails with error codes 7 and -1

Hi all,
I have been having a weird issue with my LV FPGA compilation in the last couple of days, no matter what I try to compile LV fails to generate the FPGA code files and returns with errors 7 and -1 and complains that the file is not found. This happens no matter what I am trying to compile even a VI with just a while loop. I followed the discussion forum here without any luck, also followed the NI article here and that did not help either. The error codes always get generated at the start of the Generating Intermediate files step #7 (out of 7).
Attached to this post is a screenshot of the error I am getting (error -1 just says internal error and to contact NI support), bellow is basically the error I get for error code 7
An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:
Error 7 occurred at Read from Text File in nirviGetInstantiation_cRIO-IDSel_Timer.vi->nirviGetInstantiation_cRIO-IDSel_Timer.vi.ProxyCaller
Possible reason(s):
LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.
=========================
NI-488: Nonexistent GPIB interface.
C:\NIFPGA\compilation\cRioController_8-SlotFPGA_FPGA-TriggerTest_C06156E2\IDSel_Timer.vhd
I tried to do some digging to see what could possibly be happening, and I noticed that LV is looking for the vhdl files in the wrong folder (see the line highlighted in red above), when generating the vhdl files, LV will place them inside the "source_files" folder under the compilation project, but for some reason it is trying to find them under the root folder not inside the source_files folder!!!
Does anyone have any idea why LV would be looking for these files in the wrong subfolder?
Thank you,
Aws
Attachments:
Code Generation Errors.png ‏35 KB

Hi Aws_Khudhair,
What version of LabVIEW are you using? And what version of the FPGA module? From what I found, it seems as though this is primarily an issue with LabVIEW 8.6 and 8.6.1.
http://digital.ni.com/public.nsf/allkb/A711119FE89E39E78625754E00075E92
This forum also discusses a similar issue:
http://forums.ni.com/t5/Real-Time-Measurement-and/FPGA-compile-errors-after-generating-intemediate-f...
It may also be worth repairing/reinstalling the FPGA Module and the Xilinx compile tools.
Catherine B.
Applications Engineer
National Instruments

FPGA code successfully compiled in 2010 is giving compilation error in 2014.

I have developed RS485 FPGA code and successfully compiled with LabVIEW FPGA 2010.
Later changed the software to 2014 and installed Xilinx 14.7.
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I am using a case structure with Error cluster as selector, So the case structure has 'No error' and 'Error' cases.
If I change the selector to 'True/False' then the compilation works.
Below is the error that i am getting when using Case structure with Error cluster as selector
LabVIEW FPGA: The compilation failed due to a Xilinx error. Details: ERROR:HDLParsers:1401 - "C:/NIFPGA/jobs/JyWfWcc_Gv3a9ah/NiFpgaAG_00000041_CaseStructureFrame_0001.vhd" Line 41. Object tunnel_s_error_out_2007 of mode OUT cannot be read. ERROR:HDLParsers:1401 - "C:/NIFPGA/jobs/JyWfWcc_Gv3a9ah/NiFpgaAG_00000041_CaseStructureFrame_0001.vhd" Line 42. Object tunnel_s_error_out_2007 of mode OUT cannot be read. --> Total memory usage is 190240 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings: 1 ( 0 filtered) Number of infos : 0 ( 0 filtered)

Attached FPGA_error_2014.jpg which depicts the working and 'not working' code in 2014.
In 'Not working' code,the selector terminal is error cluster.
I am able to resolve the issue just by changing the selecter terminal to boolean as in 'working code'.
But both sets of software code works fine in version 2010.
Attachments:
FPGA_error_2014.jpg ‏128 KB

Problem modifying FPGA code in an Application Builder-based system

I've inherited a working test system which uses LabVIEW FPGA, LabVIEW, Application Builder, and third party tools. The FPGA module (a FlexRIO) is responsible for generating test signals to a DUT and acquiring DUT output data. The host LabVIEW code controls the FlexRIO and acquires the test data. Application Builder is used to convert the host LabVIEW code to a Windows DLL so that it can be in turn controlled by higher level data analysis software running on Windows.
All of this currently works, and we're using it on a daily basis to test production devices.
We need to modify the FPGA operation to change the way the tests operate. We've modified the the FPGA VI to operate as we need it to and rebuilt the FPGA code (resulting in a new bit file), but subsequent runs of the test stack do not show the change to the operation of the FPGA code (the signals it is generating look exactly the same as in the original, unmodified, VI). We've tried renaming, deleting, and moving the bit file, but operation of the system is always exactly the same, even when the bit file is named differently or not located in the expected directory. We can't seem to affect the behavior we get out of the FPGA. It seems like we're not rebuilding something correctly, or that the system somehow has a copy of the old bit file stored away some place that it's using instead of the desired bit file.
We've verified that the newly created bit file is different than the original bit file, so it appears that the FPGA build process is succeeeding. I see no errors from LabVIEW when I build the FPGA code.
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It seems highly suspicious that we see the FPGA come up and run even when the bit file has been renamed or moved from the directory indicated in the "Open FPGA VI Reference". I would think that the DLL would attempt to open that file, fail to find it, and trip some sort of error dialog. But this doesn't occur, the FPGA gets loaded normally, and the test system operates as if nothing had been touched.
Previous developers were able to make this build process work, but it seems we're missing some critical step needed to actually update the code that ends up running on the FPGA.
The system is LabVIEW 2012.

The FPGA build definition has the bitfile filename hardwired into it, so the name is constant across rebuilds of the FPGA code. So we always have the same bitfile name (and consequently if we're not careful about saving the old files, then the old bitfile will be overwritten by a new build).
I could try your suggestion about the alternate calling method, but I'm hesitant about changing a build process that was known to work. It seems to me that I'm somehow not building the software correctly, as if I don't understand something about the DLL build process that's keeping the new FPGA code from being used.
To reiterate, our build process is:
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2) "Run" the FPGA VI to compile it (by the way, last night we tried a "Rebuild" on the FPGA code from the right click menu off the VI in the LabVIEW project and that also has failed to change the results)
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Error downloading and running fpga code

Hi all,
I am getting an error downloading FPGA code to fpga board on another PC. It works fine from various other development machines but will not work with my laptop. Attached is the error code dialog box that comes up when I try to run the FPGA code. Has anyone seen anything like this before?
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Dean
Attachments:
Error Code Dialog Box.PNG ‏10 KB

I guess I was a little lacking in details. All of the LabVIEW installs on all the PC's are the same. Windows service packs and security updates etc are close. My laptop has a bit extra on it with VMWare, wireless, some security software, other usb dongles for other software, etc. This only occurs with a compiled FPGA VI that I am trying to run on the FPGA with the LV front panel open. If I create windows VI and call the fpga code with an Open FPGA reference linked to a bitfile or a VI there is no problem. I have followed all the methods for connecting to the remote FPGA card. I have repeated the process with blank projects on my laptop and another PC and created the exact same code.
This is why I am asking if someone knows what the error code means to help narrow down the search. The visa check in MAX works and I can open the RIO Device Setup from the LabVIEW project.
Dean

FPGA code using too much memory? getting error 52000

Hi all,
   I'm having trouble getting some FPGA code to run. What I am trying to do with the program is acquire data using DAQmx from two fgen's, and then use an FPGA based lock-in amplifier to find the frequency of these signals and their phase difference (It's actually only a slight modification of a lock-in amplifier available on the NI site). I keep getting error 52000 when I start up the program, indicating I'm using up too much memory somewhere. I don't know why this is, as even the lowest sampling rates I give to the DAQ do not keep this problem from happening. Could someone look at my code to see whats going on?
Thanks,
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Attachments:
LIA_SSTL.lvproj ‏90 KB

I am using a PXI-7852R card in a PXI-1033 chassis, all connected to my comp through a PCI bridge. I'm also using a PXI-6115 data acquisition card, which is feeding data to the FPGA.
Sorry for not attaching the VI's, I thought they were contained within the llb. Here they are.
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Attachments:
LIA_FPGA.vi ‏285 KB
LIA_Host.vi ‏2346 KB

Rt - unable to deploy model and fpga code

hi all,
we are having trouble getting our code to deploy to a rt target and fpga
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system:
Host : windows 7, NI Labview 2014, MIT / Vertistand installed
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Hi JK,
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FPGA Interface VIs and Functions
http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgahost/fpga_interface_palette/
Transferring Data between the FPGA and Host (FPGA Module)
http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgaconcepts/fpga_data_transfer_overview/
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Kevin W.
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Running cRIO/FPGA code locally

So I'm currently writing code that will have to run on a cRIO (both the real time processor and the FPGA). Is there a way I can run it on my computer without being hooked up to the hardware? I don't have easy access to to hardware and would really like to test the behavior of my code.
Thanks.
Solved!
Go to Solution.

Hi,
You can create a cRIO in your LV project without having the hardware, you can compile the FPGA code and run it in simulation mode too, but you cannot run the RT code.
Christian

How do I control a digital output on NI9144 FPGA with fpga code running on NI9082.

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Are there any good code examples around that someone can point me to?
Thanks for the help.

Hi, you can include trigger conditions (digital, or analog) on your FPGA VI and connect directly the I/O from module to module (analog with analog & digital with digital), however, if the chassis are meant to be at different locations the cable used to connect the ports is equals the length in between each device and that could degrade the signal if we are taking about a couple meters or kilometers. The most reasonable way to send/receive data from great distances is through ethernet using a regular communication protocol (such as TCP/IP, network streams, network shared variables...etc).
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I have a pretty "urgent" problem here:
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Thanks for the reply,
I hope the file attached helps. It is labview 2013 - I just increased the DMA Depth to 5000 (from 1024), because I thought this might be the problem - it was not - so that can be ignored.
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Thanks

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I have some code I wrote for FPGA which, by itself, works fine. I tried to use "Open FPGA VI Reference" as part of a previous (non-FPGA based) VI. However, I find that the full code only works on alternate executions. I thought this may be because the FPGA VI is not being reset properly. However, I have used "Close FPGA VI Reference" and chose "Close and Reset" and the problem remains.
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Hi Gary,
I hope you are doing well today! What version of LabVIEW FPGA are you using? When you say you are doing 'alternate executions', what exactly do you mean? Do you run your host VI, stop it and then run it again? Have you tried just using Close instead of resetting the FPGA VI? Also, what are you using the reference for? What are you invoking? It would, also, be better if you post a screenshot of your VI.
Adnan Zafar
Certified LabVIEW Architect
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