FPGA Compilation Error (Some signals were not properly constrained in the design)

Attempting to compile even simple FPGA VIs is returning in failure for me, and I'm not sure why. This is on windows 7, 32 bit, Xilinx 14.4, LabView 2013, for sbRIO-9632.
"Some signals were not properly constrained in the design." in the summary.
and
"Failed to load library libPort_ExecLoader.dll because of The specified procedure could not be found." in the Xilinx log.
Can anyone help? Many thanks!
Attachments:
summary.txt ‏1 KB
XilinxLog.txt ‏17 KB

Hello everyone !
I use a cRIO-9103 for my project and I attempted to compile a new VI for the FPGA. The former code compiled without problem, but the new one failed with the error "Some signals were not properly constrained in the design". I read the issue that was given in this topic, but the strange thing is that I just added a while loop in my old program to make my new one. 
I joined to this message the new programm of the FPGA and the Xilinx log (I use Xilinx 10.1). The While Loop which causes problems is called "Traitement des informations envoyées par la centrale inertielle (IMU)". Can someone save me please ?  ^^
Thanks !
Attachments:
Init_9401.vi ‏279 KB
XilinxLog 10_05_2014 16_00.txt ‏993 KB

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