FPGA Compile Error due to error in mapping process

Received the following error while trying to compile a FPGA VI on a PC. (Refer to attachment for details). My PC has a fresh installation of English Windows 2000 with sp4. No other software is installed except LabVIEW 8.2 & FPGA Module 8.2 & NI-RIO.
I have checked this KB and confirmed that regional settings are English. But the error still exists. I tried compiling the same VI on my laptop with Windows 2000 sp4 and it was successful. Can someone help me? Thank you very much!
FPGA Compile Error When Compiling LabVIEW FPGA VI
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.
Design Summary
Number of errors : 17
Number of warnings : 8
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
Message Edited by maimai on 01-08-2007 01:00 AM
Attachments:
FPGA Compile Error.txt ‏8 KB

Hello,
The key will of course be to isolate differences between your machines.
I wonder if the following more specific language setting could be the lingering problem. LabVIEW is a non-unicode program, and there is a language setting in Windows (at least XP) specifically for non-unicode programs. Try the following (or it's Win2K equivalent) if you haven't already:
0. Open "Control Panel"
1. Open the "Regional and Language Options"
2. On the Advanced tab, choose English (United States) from the drop-down menu under the top section "Language for non-Unicode Programs"
- This language setting is different from the setting on the "Regional Options" tab.
Any other differences you can isolate would be potentially insightful - if you have the same software versions installed in the same order on both machines, we may be looking for something a bit subtle, such as the suspected language setting.
Best Regards,
JLS
Best,
JLS
Sixclear

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Fpga compilation xilinx error 'Process "Map" failed' - 'unroutable situation'

When I try to compile a Labview fpga project on our new system, it fails with the following error summary (the full Xilinx log is attached):
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:LIT:536 - IBUF symbol "aUserGpio<1>_IBUF" (output
signal=aUserGpio<1>_IBUF) has the attribute IOBDELAY set to value NONE and it
is driving an IODELAY. If the IOBDELAY attribute is on the driving PAD, it
has precedence over the IBUF one. Either the constraint or the design need
modification to prevent an unroutable situation.
Errors found during logical drc.
Design Summary
Number of errors : 1
Number of warnings : 349
Process "Map" failed
Start Time: 10:31:49 AM
End Time: 10:55:32 AM
Total Time: 00:23:43
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview 2011 version 11.0
Labview FPGA module 11.0.0
FPGA compilation tools (Xilinx12_4)
NI FlexRIO Adapter Module Support 2.2.0
NI-RIO 4.0 (FlexRIO 2.1.0)
Xilinx DRAM compilation bug fix patch from NI article id 5E4FNCDP
Xilinx clock bug fix patch from NI article id 5GFAB7DP
replaces c:\NIFPGA\programs\Xilinx11_5\ISE\xilinx\lib\nt\libPlXil_Clocks.dll; The installed version is c:\NIFPGA\programs\Xilinx12_4-> Manually copied the dll to the installed version
The Project uses the 5761 low speed clip and a DRAM FIFO.
I tried to compile it before installing any patch, after installing the DRAM patch, and after installing both patches and always got a Xilinx error after ~10 minutes compile time. The error summary shown above and the attached Xilinx log are from compiling with both patches installed.
It compiled correctly on our older system:
Hardware:
NI PXIe-1082 Chassis
NI PXIe-8133 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview2011version10.0.0
LabviewFPGAmodule10.0.0
FPGAcompilationtools (Xilinx11_5)
NIFlexRIOAdapterModuleSupport2.1.0
NI-RIO3.5.1 (FlexRIO1.5.0)
XilinxDRAMcompilationbugfixpatchfromNIarticleid5E4FNCDP
Any help / suggestions greatly appreciated,
Fabrizio
Attachments:
XilinxLog.txt ‏1482 KB

Hi Torpedotown,
Can you tell me what version of FlexRIO Adapter Module Support you are using?
The 5761 Low Speed CLIP has a constraint that doesn't work properly with some versions of the compilation tools. In order to solve this you should be able to upgrade to our latest version of FAM support, or go change the constraint manually.
For the latest version of FAM support, go to http://ni.com/info and enter code "famsoftware"
If you've modified constraint files before and feel comfortable doing it yourself, let me know and I can provide you with the details on how to do that.
Thanks!
National Instruments
FlexRIO & R-Series Product Support Engineer

LabVIEW FPGA: The compilation failed due to a xilinx error

I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2013.The code had compilated successfully in labview2012. Any suggestions on what is causing this issue?
Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 29: Formal <cparametersignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaSetOutputDataEnable.vhd" Line 37. cparametersignal is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 21: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd ignored due to errors
-->
Total memory usage is 204688 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed
Compilation Time
Date submitted: 2014/2/26 18:15
Date results were retrieved: 2014/2/26 18:17
Time waiting in queue: 00:06
Time compiling: 02:02
- PlanAhead: 01:16
- Core Generator: 00:00
- Synthesis - Xst: 00:35
Solved!
Go to Solution.

I have got the same error, Have you solved this error?
What you have done?
jasonneu wrote:
I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2013.The code had compilated successfully in labview2012. Any suggestions on what is causing this issue?
Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 29: Formal <cparametersignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaSetOutputDataEnable.vhd" Line 37. cparametersignal is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 21: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd ignored due to errors
-->
Total memory usage is 204688 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed
Compilation Time
Date submitted: 2014/2/26 18:15
Date results were retrieved: 2014/2/26 18:17
Time waiting in queue: 00:06
Time compiling: 02:02
- PlanAhead: 01:16
- Core Generator: 00:00
- Synthesis - Xst: 00:35
Mahran

FPGA Compile error - Actual of formal out port cout cannot be an expression

Details:
ERROR:HDLCompiler:192 - "C:\NIFPGA\jobs\BPO5kq2_O6tyN2U\OC4_Sine_Cosine_LUT_Constant_Amplitude_dash_optimised_vi_c.vhd" Line 1408: Actual of formal out port cout cannot be an expression
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\BPO5kq2_O6tyN2U\OC4_Sine_Cosine_LUT_Constant_Amplitude_dash_optimised_vi_c.vhd" Line 69: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\BPO5kq2_O6tyN2U\OC4_Sine_Cosine_LUT_Constant_Amplitude_dash_optimised_vi_c.vhd ignored due to errors
-->
The compilation gets to the "Estimated device utilisation" stage but then stops shortly after with a compilation error.
The Line in question (1408) relates to the output of a "Reinterpret FXP" node with the text
cOut => (others => '0'),
in the port map portion of the code. This corresponds to the output of the FXP reinterpret node being directly connected to an indicator in a sub VI whose output is then input directly to a high thoughput multiply node. The code is part of a sinus cosinus LUT I have programmed. It used to compile no problem but I think I know where the problem is. In one instance I only utilise the Sinus output of the algorithm and theoretically, Xilinx can optimise away the Cosinus part. I have two instances of this VI in my code and looking at the one NOT generating errors, the output is associated with a Cosinus indicator.
cOut => s_Cosine_2434,
It would seem that the pathway is essentially optimised away but the Xilinx compiler has a problem with the indicator being present on the sub-VI but the idnicator not being utilised anywhere. As such, the cOut gets set to an invalid value. I assume the immediate proximity of the FXP Reinterpret to the output of the sub-VI is an important aspect of this problem.
I think I know enough now to fix this problem (manually remove the path by duplicating the sub-vi) but this is perhaps a useful feedback for future bugfixes in the FPGA module. This isn't the first time this kind of incorrect code removal has given me problems but it's the first time I've been able to clearly locate the problem.
Shane
Say hello to my little friend.
RFC 2323 FHE-Compliant
Solved!
Go to Solution.

I am currently attempting a compile after changing some things.
Just a side question. Is this particular to the Reinterpret node or are other "pink nodes" also affected by this? If I don't connect the output of a high throughput add, will it result in the same behaviour?
PS OK, it seems to be compiling now. I managed to juggle around the nodes a bit in my sub-VI to make sure the "reinterpret" is not the last node before the indicator. It seems to be compiling now. A question which is in my head at this time is: Does the "reinterpret" node prevent anything before it from being optimised away by the Xilinx compiler? Are there other nodes which cannot be removed, even if the outputs are not being used? This would immediately seem to suggest to me that such nodes need to be as close to the source as possible in order to reduce the amount of code which cannot be removed as "dead code" during the Xilinx compile process.
Say hello to my little friend.
RFC 2323 FHE-Compliant

FPGA Compile Error: Timing Violation

All,
I've got an issue here I've been struggling with for a couple days now. I'm trying to implement a very watered down Kalman filter in the FPGA (I wanted it to run faster than I had it running in the RT.) After quite a bit of optimization, I'm still stuck to no avail. This first thing I tried was simply using the filter I had and changing my math to use fixed point instead of floating point. However this was about 20 operations in series (multiplies, adds, subtracts, and one inverse, (( what's the most efficient way to do an inverse in the FPGA? ))) and the FPGA did not like that at all. So I tried to pipeline the operation. Now mind you this isn't a true pipline because new data cannot be introduced to the pipe in each cycle (I need the output of the last cycle before I can introduce new data,) but I was simply trying to split up the math and have the FPGA only do part of it on each iteration of the while loop, because I thought the FPGA would be able to run this filter way faster than I needed to.
Here's the error I'm getting...
Status: Compilation failed due to timing violations.
Click the Investigate Timing Violation button to display the Timing Violation Analysis window.
Device Utilization
Total Slices: 59.0% (12084 out of 20480)
Flip Flops: 28.5% (11692 out of 40960)
Total LUTs: 45.9% (18788 out of 40960)
Block RAMs: 0.0% (0 out of 40)
Timing
MiteClk (Used by non-diagram components): 33.04 MHz (69.24 MHz maximum)
40 MHz Onboard Clock: 40.41 MHz (30.29 MHz maximum)
Actual Xilinx Options
Synthesis Optimization Goal: Speed
Synthesis Optimization Effort: High
Map Overall Effort Level: High
Place and Route Overall Effort Level: High
Start Time: 6/6/2010 10:11:47 PM
End Time: 6/6/2010 10:57:33 PM
And then when I try to investigate the timing violations the "Timing Violation Investigator???" gives me this!!:
Possible reason(s):
An internal error occurred. Please try again or contact National Instruments.
Details:
Error Code --> -61499
Error Text --> <APPEND>
Additional Information: There is no matching tag in Xilinx twx file
There is no matching tag in Xilinx twx file
Also,
I was able to successfully run the "Timing Violation Investigator" a couple times. The first time it pointed to a multiply operation which i replaced with high throughput math and pipelined. The second time it pointed to "non-diagram components," how am I supposed to fix that?
I've attached the code and the xflow.log! Thanks for your time!
Thanks!
Ken
Attachments:
FPGA.zip ‏778 KB
xflow.txt ‏1138 KB

Hey Ken!
If you hit the "Investigate Timing Violation" button and go to the analysis page, it looks like there are a couple of math functions that are taking longer than expected.
If you replace them with high-throughput math equivalents (from the FPGA Math & Analysis palette) and manually configure the inputs and output FXP word/integer lengths, you might be able to get them within the timing requirements.
Let me know if that works!
Caleb Harris
National Instruments | Mechanical Engineer | http://www.ni.com/support

FPGA: compilation error: size of concat operation is different than size of the target

Today I got an error, for which I couldn't find a solution.
I use the PXI-7813R FPGA, with Xilinx tools 10.1
At compilation, the error I get is:
Compilation failed due to a Xilinx error.
Details:
ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 301. Size of concat operation is different than size of the target.
ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 372. Size of concat operation is different than size of the target.
-->
Total memory usage is 185944 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesis" failed
Start Time: 18:25:26
End Time: 18:28:54
Total Time: 00:03:27
What can cause a concat size difference?

This is by the way the configuration:
Project: FPGAWrapperMG100125AOD.lvproj
Target: FPGA Target (RIO0, PXI-7813R)
Build Specification: fpga_integrator_AOD_random_access
Top level VI: fpga_integrator_AOD_random_access.vi
Compiling on LabVIEW FPGA Compile Cloud Service
Compilation Tool: Xilinx 10.1
Start Time: 05.07.2011 19:06:12
Run when loaded to Fpga: FALSE
Xilinx Options
Design Strategy: Custom
Synthesis Optimization Goal: Area
Synthesis Optimization Effort: Normal
Map Overall Effort Level: Default Xilinx setting
Place and Route Overall Effort Level: High
JobId: FNW72uPWorking Directory: C:\NIFPGA\compilation\FPGAWrapperMG100_FPGATarget_fpgaintegratorAO_9D5B4237
The Xilinx log is attached.
Attachments:
XilinxLog.txt ‏80 KB

The compilation failed due to a Xilinx error (410)

Hi Peeps,
I'm trying to compile my FPGA code with the Cloud Compile Service. I have an FPGA code that compiles without any problems. When I put a DMA FIFO Node into this code, I get the following Xilinx compiler error:
ERROR:HDLCompiler:410 - "/opt/apps/NIFPGA/jobs/CSD2awO_GQdD63p/NiFpgaAG_0000050c_CaseStructureFrame_0001.vhd" Line 211: Expression has 66 elements ; expected 50
Netlist NiFpgaAG_0000050c_CaseStructureFrame_0001(vhdl_labview) remains a blackbox, due to errors in its contents
The code compiles well without the DMA Node. The DMA is a Target to Host DMA, 1023 element long (Block Memory), the type of the elements is U32.
There are other thing on the block diagram as well. When I copy this SCTL into a new VI without anything else in it, it compiles without problems, regardless if the DMA Node is there.
Please find the VI snippet and the error summary attached.
Any ideas are welcome.
Cheers,
Norbert
Solved!
Go to Solution.
Attachments:
FPGA.png ‏92 KB
Error Report.txt ‏36 KB

So the problem seems to be resolved...
I deleted the DMA FIFO node from the block diagram and added it again. After about 40 minutes I had a successful compilation. Weird.

FPGA compile error

Good Afternoon,
I am getting a compile server error that I do not know how to track down. The server is set up and working fine (LV 8.6 cRIO, FPGA) I can send over on FPGA file and it compiles fine. When the second is sent, the compile request is received and starts, but a quickly get the following pop-up:
"Status: Compilation failed due to a Compile Server error.
Regenerating IP...
ERROR:coreutil - Failure to set parameters on core: Illegal combination: Port A
   Width and Port A Depth
ERROR:coreutil - Failure to generate output products
ERROR:coreutil - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.
   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.
ERROR:sim:57 - Error found during generation
Start Time: 2/17/2009 10:22:28 PM
End Time: 2/17/2009 10:22:54 PM"
I am aware that something is amiss in my FPGA VI, but I am unsure what the above messages are telling me to look at. Any ideas? It was working/compiling, but I changed the cRIO backplane configuration, removing some inputs and adding different ones.
Message Edited by Mellobuck on 02-17-2009 09:51 AM
Data Science Automation
CTA, CLA, CPI
SHAZAM!
Solved!
Go to Solution.
Attachments:
FPGA error.JPG ‏63 KB

Xilinx doesn't support a depth of 1. If possible
carry on using a depth of 8 or use some other "register" to hold the
value such as locals, globals, fifos, feedback nodes, etc. Have a look at the following:
Why Won't FPGA Code with a Memory Depth of 1 Compile?
Adnan Zafar
Certified LabVIEW Architect
Coleman Technologies

Fpga compile error Port width mismatch

When I try to compile a FPGA vi, the following error occurs.
LabVIEW FPGA: The compilation failed due to a Xilinx error.
Details:
ERROR: [Synth 8-549] port width mismatch for port 'cEIOParameter0Signal': port width = 32, actual width = 24 [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_0000051e_SequenceFrame.vhd:41]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_0000051e_SequenceFrame' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_0000051e_SequenceFrame.vhd:21]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_0000051d_CaseStructureFrame_0002' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_0000051d_CaseStructureFrame_0002.vhd:33]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_0000051a_SequenceFrame' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_0000051a_SequenceFrame.vhd:34]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_00000514_CaseStructureFrame_0001' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_00000514_CaseStructureFrame_0001.vhd:41]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_00000513_CaseStructureFrame_0000' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_00000513_CaseStructureFrame_0000.vhd:50]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_00000510_CaseStructureFrame_0000' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_00000510_CaseStructureFrame_0000.vhd:143]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_00000507_CaseStructureFrame_0001' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_00000507_CaseStructureFrame_0001.vhd:146]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_000004ff_WhileLoop' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_000004ff_WhileLoop.vhd:157]
ERROR: [Synth 8-285] failed synthesizing module 'DM_dash_1575_ModuleResource_vi_colon_Clone19' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/DM_dash_1575_ModuleResource_vi_colon_Clone19.vhd:144]
ERROR: [Synth 8-285] failed synthesizing module 'niFpgaMDKSupportARV_vi_1_colon_Clone18' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/niFpgaMDKSupportARV_vi_1_colon_Clone18.vhd:143]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_Manager' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_Manager.vhd:96]
ERROR: [Synth 8-285] failed synthesizing module 'TheWindow' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/TheWindow.vhd:196]
ERROR: [Synth 8-285] failed synthesizing module 'toplevel_gen' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/toplevel_gen.vhd:110]
Finished RTL Elaboration : Time (s): cpu = 00:00:53 ; elapsed = 00:01:04 . Memory (MB): peak = 861.121 ; gain = 715.336
ERROR: [Common 17-39] 'source' failed due to earlier errors.
INFO: [Common 17-83] Releasing license: Synthesis
1738 Infos, 30 Warnings, 2 Critical Warnings and 14 Errors encountered.
synth_design failed
::ERROR: [Common 17-39] 'source' failed due to earlier errors.
while executing
"source -notrace {./.Xil/Vivado-9588-/realtime\toplevel_gen.tcl}"
invoked from within
"synth_design -top "toplevel_gen" -part "xc7k70tfbg676-1" -flatten_hierarchy "full""
(file "C:/NIFPGA/jobs/Riuys15_TD5ekmx/synthesize.tcl" line 25)
invoked from within
"source "C:/NIFPGA/jobs/Riuys15_TD5ekmx/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Thu May 07 10:24:37 2015...
I am not sure what the error is all about. Could someone help me?

It's usually better to take a look at where the code failed to compile in the process than trying to read through those logs. In future cases, you'll want to show that information as well.
Depending on your hardware, you might have been able to see the compile happen simply by hitting compile again.

Compilation failed due to timing violations, Getting Xflow error and resources over use.

Hi,
I am extensively using Fixed point math library functions which i have downloaded from NI website in my FPGA application.I am getting following errors while compiling the code.
I would like to know is there any limitations in using fixed point functions?
I am configuring all funtions as a 64 bit word length and 32 bit integer length in cofig parameter set up and all are outside the timed loop.
Apart from below error it is occupieng LUT's 300% in one simple VI (mathematical calculations using fixed point functions).
So i would like to know is there any way to optimize the code?.
Status: Compilation failed due to timing violations.
The compile process reported a timing violation.
Suggestions for eliminating the problem:
* For Timed Loops with timing violations
      - Reduce long arithmetic/combinatorial paths
      - Use pipelining within Timed Loops
      - Reduce the number of nested case structures
* Reduce clock rates if possible
* Recompile
Refer to the LabVIEW Help for more information about resolving compilation errors. Click the Help button to display the LabVIEW Help.
Compilation Summary
Device Utilization Summary:
   Number of BUFGMUXs                        2 out of 16     12%
   Number of External IOBs                 214 out of 484    44%
      Number of LOCed IOBs                 214 out of 214   100%
   Number of MULT18X18s                     69 out of 96     71%
   Number of SLICEs                       4387 out of 14336 30%
Clock Rates: (Requested rates are adjusted for jitter and accuracy)
Base clock: 40 MHz Onboard Clock
      Requested Rate:      40.408938MHz
      Achieved Rate:       36.974044MHz    <<<=== Timing Violation

lion-o wrote:
The Fixed Point Library is certainly not a demo, and we encourage you to use it extensively.
Really? "Demo" is perhaps too strong a word, but the NI Labs page says that the toolkits there "aren't quite ready for release" and are "experimental prototype"s. My understanding was that they work, but are only meant to show potential future products and get feedback on them. If this is not the case, perhaps the wording needs to be changed.
I know I wouldn't want to be using something throughout my code and then find out that it is not supported when the next LV version came out because it was only a prototype. Can you promise support into the future for these? If you can't, that should be clearly stated.
Try to take over the world!

Compilation error - FPGA NI PXI-7951R board - ERROR: Xst: 2472 - Top module Puma15Top was not found.

I'm trying to compile a "user CLIP socket" for the NI PXI board - 7951R which has a Virtex-5 LX30 FPGA from Xilinx, but I got the bellow message from NI Compiler, this message is in error report Xilinx.log.
It says that module Puma15Top was not found.
But this module is a NI property and is automatically compiled by NI Compiler.
The compiler automatically generates these files (Puma15Top...) that are passed to the compiler of Xilinx. The Puma15Top files are in the path, i.e: C: \ NIFPGA \ compilation \ Told_F_I_CC5DC260 \ source_files.
This folder name is automatically generated by labview (Told_F_I_CC5DC260) for each different project or compilation.
So I have no way to configure in CLIP files where it'll be Puma15Top, once the path is automatically generated during compilation by Labview.
Does anyone have any idea how to solve this problem? Or have you experienced some like this?
Following error log:
### XstSynthesis ###
Puma15Top
Reading design: Puma15Top.prj
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/NIFPGA/jobs/Cm9xA8x_LaF6U1d/CLUC001_Conf.vhd" in Library work.
Entity <CLUC001_Conf> compiled.
Entity <CLUC001_Conf> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/NIFPGA/jobs/Cm9xA8x_LaF6U1d/CLUC001_CLIP.vhd" in Library work.
Entity <CLUC001_CLIP> compiled.
Entity <CLUC001_CLIP> (Architecture <rtl>) compiled.
Entity <CLUC001_CLIP> (Architecture <behavioral>) compiled.
ERROR:Xst:2472 - Top module <Puma15Top> was not found.
ERROR:Xst:2469 - Please specify the correct library via the -work_lib switch.
-->
Total memory usage is 149596 kilobytes
Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
Process "Synthesis" failed
Thanks in advanced!

Hi Guilherme,
Thanks your suggestion, I upgraded NI-RIO to 13.1.1 version but the problem persists, as shown below:
Project: T_old.lvproj
Target: F (RIO0, PXI-7951R)
Build Specification: I_2
Top level VI: I.vi
Compiling on local compile server
Compilation Tool: Xilinx 11.5
Start Time: 2/9/2014 18:03:51
Run when loaded to Fpga: FALSE
JobId: z8Cq8B4
Working Directory: C:\NIFPGA\compilation\Told_F_I2_F3177096
Compilation failed due to a Xilinx error.
Details:
ERROR:Xst:2472 - Top module <Puma15Top> was not found.
ERROR:Xst:2469 - Please specify the correct library via the -work_lib switch.
-->
Total memory usage is 149596 kilobytes
Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
Process "Synthesis" failed
Start Time: 18:03:51
End Time: 18:05:19
Total Time: 00:01:27,414
Best,
JEMP

Compilation failed due to a compile server error

I was using LABView 8.0 with RT and FPGA module without problems.
I updated windows on 2006 April 18th and now I cannot compile any FPGA VI. Even the older one I compiled with the same computer previously.
When I take EXACTLY the same project to another computer, it compiles just fine and when I take the bitfile back, my corrupted system can run with the bitfile.
I fear the problem is with windows. I reinstalled LABView TOTALLY and still have the same error when trying to compile.
According to the knowledge base I checked the HKEY and it doesn't change anything.
Here is the error message:
Status : compilation failed due to a Compile Server error
Error -61499 occured at nirviExtractVHDLHierarchy.vi when called from nirviBuildprjFile.vi
Possible reason(s)
LABView FPGA : An internal software error in ALBView FPGA Module has occured. Please contact NI support
Details : Error 7 occured at Open File reading C : \ NIFPGA80\srvrtmp\localhost\Eight...name of the bitfile ...\scripts\toplevel_gen_synth_lvfpga.txt
Note : I checked this folder, it doesn't exist, thus it has never been created like the previous. After April 18th, not any new folder has been created.
Possible reasons : File moved or deleted, incorrect filepath,...
NI-488 : Non-existent board
Note : I have nor use none of this nowhere !
Start time - Stop time : 12 seconds

In order to try and isolate the problem can you perform a few tests.
1) Set up a remote compile and use the machine that is not working as the client and the machine that is working as the server.
1.a) You can configure the client machine to use another machine as the compile server by going to Tools>>FPGA Module Options...>>Configure Compile Settings and change the machine from 'localhost' to the machine that you want to act as the server.
1.b) On the server machine open the Compile Server manually by going to the Windows Start Menu>>All Programs>>National Instruments>>LabVIEW 8.0>>LabVIEW FPGA Utilities>>Compile Server
1.c) Try and compile the VI. It should generate code on the client machine and send the generated code to the server. Wehn the server receives the code it will compile it and return the bitfile when complete.
2) Set up a remote compile and use the machine that is not working as the server and the machine that is working as the client.
2.a) Follow the instructions in part 1, but switch the client and server machines.
These tests should help us isolate if the problem is with the Compile Server, or the code generation.
Regards,
Joseph D.
National Instruments

CRIO FPGA Compilation Error : xilinx 21955

Hi all,
I tried to compiled my first "real" application today, and how unexpected in the NI world: it didn't work !
I got myself a nice error message from xilinx :
Regenerating IP...
ERROR:coreutil - Failure to set parameters on core: Illegal combination: Port A
   Width and Port A Depth
ERROR:coreutil - Failure to generate output products
ERROR:coreutil - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.
   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.
ERROR:sim:57 - Error found during generation
The xilinx page did not help me so far, and I don't find any reference of the "Illegal combination: Port A Width and Port A Depth" error which is probably the key to my situation.
The app. is not so complex (yet) and make some use of the "Memory" objects... maybe it's about that.
Anyway, I'll welcome any observation, advice (or solution) ;-)

Hi all,
           I think i am facing with a similar error...
My error description is:
Release 8.1.03i - Xilinx CORE Generator IP_I.20
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Regenerating IP...
occurred during initialization of Vnot reserve enough space for object heanot create the Java virtual machineERROR:coreutil - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.
   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.
I cant find any help with the above link... Can any help me in this issue...??

Compilation failed due to a Xilinx error

I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2011. This code runs on a FlexRIO (PXIe-7962R) with an adapter module (NI 5751). The issue comes when using the IDELAY clip node to synchronize the start of collection between two flexrio/5751 pairs. The error message mentions "internal_IDELAY_CLIP_DataOut) has DELAY_SRC set to either I or IO but IDATAIN is not driven by an IBUF". When we faced this issue before it was solved by following the steps in the following knowledge base article:
http://digital.ni.com/public.nsf/allkb/BBD7A87F2ADC2028862577FB005F6B19
These patches only mention LabVIEW 2010 but since I'm using LabVIEW 2011 they don't apply. Any suggestions on what is causing this issue? I verified that if I remove this clip node it compiles successfully.
Andy Brown
Averna

Hi Andy,
As mentioned in the KB "this issue is caused by a bug in the Xilinx ISE compiler". It is not related to the version of LabVIEW, but it is related to the version of your compiler. Which version of Xilinx compiler are you using? (Check the contents of the C:\NIFPGA\programs folder). If you are still using the 11.5 version then you can still use the patch even if you are running LabVEW 2011.
Sev K.
Applications Engineering Specialist | CLA
National Instruments

FPGA Compile Error due to error in mapping process

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