FPGA Compile Error: Timing Violation

Question

All,
I've got an issue here I've been struggling with for a couple days now. I'm trying to implement a very watered down Kalman filter in the FPGA (I wanted it to run faster than I had it running in the RT.) After quite a bit of optimization, I'm still stuck to no avail. This first thing I tried was simply using the filter I had and changing my math to use fixed point instead of floating point. However this was about 20 operations in series (multiplies, adds, subtracts, and one inverse, (( what's the most efficient way to do an inverse in the FPGA? ))) and the FPGA did not like that at all. So I tried to pipeline the operation. Now mind you this isn't a true pipline because new data cannot be introduced to the pipe in each cycle (I need the output of the last cycle before I can introduce new data,) but I was simply trying to split up the math and have the FPGA only do part of it on each iteration of the while loop, because I thought the FPGA would be able to run this filter way faster than I needed to.
Here's the error I'm getting...
Status: Compilation failed due to timing violations.
Click the Investigate Timing Violation button to display the Timing Violation Analysis window.
Device Utilization
Total Slices: 59.0% (12084 out of 20480)
Flip Flops: 28.5% (11692 out of 40960)
Total LUTs: 45.9% (18788 out of 40960)
Block RAMs: 0.0% (0 out of 40)
Timing
MiteClk (Used by non-diagram components): 33.04 MHz (69.24 MHz maximum)
40 MHz Onboard Clock: 40.41 MHz (30.29 MHz maximum)
Actual Xilinx Options
Synthesis Optimization Goal: Speed
Synthesis Optimization Effort: High
Map Overall Effort Level: High
Place and Route Overall Effort Level: High
Start Time: 6/6/2010 10:11:47 PM
End Time: 6/6/2010 10:57:33 PM 
And then when I try to investigate the timing violations the "Timing Violation Investigator???" gives me this!!:
Possible reason(s):
An internal error occurred. Please try again or contact National Instruments.
Details:
Error Code --> -61499
Error Text --> <APPEND>
Additional Information: There is no matching tag in Xilinx twx file
There is no matching tag in Xilinx twx file
Also,
I was able to successfully run the "Timing Violation Investigator" a couple times. The first time it pointed to a multiply operation which i replaced with high throughput math and pipelined. The second time it pointed to "non-diagram components," how am I supposed to fix that?
I've attached the code and the xflow.log! Thanks for your time!
Thanks!
Ken 
Attachments:
FPGA.zip ‏778 KB
xflow.txt ‏1138 KB

Answer 1

Hey Ken!
If you hit the "Investigate Timing Violation" button and go to the analysis page, it looks like there are a couple of math functions that are taking longer than expected.
If you replace them with high-throughput math equivalents (from the FPGA Math & Analysis palette) and manually configure the inputs and output FXP word/integer lengths, you might be able to get them within the timing requirements.
Let me know if that works!
Caleb Harris
National Instruments | Mechanical Engineer | http://www.ni.com/support