FPGA Contractor in Denver/Boulder Area

I am looking for a Labview Programmer in the Denver/Boulder/Ft Collins area of Colorado that has previous experience with LabView FPGA, preferrably on the CompactRIO platform. We are trying to implement a Dual Chronometry pulse counting mechanism on the CompactRIO platform with several devices providing pulse stream inputs. If you are interested and have the experience, please e-mail me at [email protected]
Thanks

You should post this on the LabVIEW Job Openings board.
p.s. Are you the old MicroMotion? If so, I'm right across the street.
Message Edited by Dennis Knutson on 05-01-2007 03:46 PM

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Denver Taxes are reported wrong on W2

Hi.
There is some difference in the W2 form that is generated for Employees belonging to Denver personal area and for other employees not belonging to Dever (say Birmingham).
As far as Dever PA is concerned only taxes in wage type /401 and /701 is getting reported in W2 and not those in wage type /451 and /751.
Where as for other Personnel Area (For ex Birmingham) all the taxes in wage type /401,/451,/701 and /751 is getting reported in W2.
Any idea what the issue might be.
Thanks,
Sriram

Can you check Recon Report for those employees.
Is mapping properly done which boxes should be displayed.
Try to test in PU19 (Test Mode)
Thanks,
Chaithanya

Any Contractors in Columbus, Ohio area?

Just had a call from a headhunter looking for a APEX developer to work for a contract project ( I am not looking for contract work, and can't relocate to Ohio at this time):
His contact info is:
William Roberson
Assistant Vice President
Mid West Regional Staffing
[email protected]
312-558-9500
Fax: 312-525-8076
Job description:
ID: 111292-1 Status:Open Submitted:12/6/2007 LOB:K - RETAIL FINANCIAL SERVICES
Summary Details Candidates Notes
Summary InformationSummary Information
Type: Contract-US
Labor Category: IT - US
Procurement Type: Staff Augmentation
Admin Cost Center: B-0805-013810
Billing Cost Center: B-0805-013810
Billing Cost Center Num: 0805-013810
Contractor Work Location: 02936 - 3415 Vision Drive
Billing Location: 02936 - 3415 Vision Drive
Request Name: CC-RPM Apex Development
Status: Open
Submitted: 12/6/2007 12:47:15 PM PST
Has Assignments: No
Position InformationPosition Information
Position: Applications Development - Data Warehouse
Position Code:
Qty: 1 !
Ant. Start Date: 12/17/2007 !
Duration: 5 Months 1 Day< 1 Week2 Weeks< 1 Month1 Month2 Months3 Months4 Months5 Months6 Months7 Months8 Months9 Months10 Months11 Months12 MonthsOther... !
Hrs/Wk: 40.00
VMO Owner: ALLENDER, WILLIAM !
Estimated Cost:
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Job Family Description: Responsible for the design, development, coding, testing, debugging and documentation of applications to satisfy the requirements of one or more user areas. May include hands-on new development as well as support, maintenance or enhancement of existing applications. Works closely with client management to identify and specify complex business requirements and processes. Researches and evaluates alternative solutions and makes recommendations.
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Region: Ohio ArizonaCaliforniaDC/VA/MDDelawareFloridaIllinoisMassachusettsMissouriNew York/New JerseyOhioTexasCanada
Level: Level 5 - Advisory Level 2 - NoviceLevel 3 - IntermediateLevel 4 - LeadLevel 5 - AdvisoryLevel 6 - Senior Manager
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*Either skills or additional skills are required Skills: Skill Required Importance Level Last Used Experience
SQL Yes 2 Intermediate 7-8
Oracle Yes 4 Intermediate 7-8
PL/SQL Yes 3 Intermediate 7-8
Additional Position Requirements: APEX Development Experience required.
*Skills have been configured as Required on the Request Type, Skills or Additional Skills is required.
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Intent to Hire: Yes
Roles and Responsibilities: Design, Develop and maintain applications for Customer Care reporting needs.

My APEX Blog: http://inside-apex.blogspot.com
The ApexLib Framework: http://apexlib.sourceforge.net
The APEX Builder Plugin: http://sourceforge.net/projects/apexplugin/

Bad or No signal in Denver/Thornton area

Is anyone else having signal problems with their new iphone? I am dropping calls or unable to make calls from my office or home. I didn't have this problem with the original iphone.

I'm having the same problem. I'm in Aurora and have driven all over now. I just got the phone yesterday but if 3G is on I can't make or receive calls, although data generally works. However sometimes its slower than edge. I love the iphone but have spent all day talking to ATT and Apple. I'm seriously considering taking it back because Apple just blames ATTs network and ATT blames the phone. I took the phone to the AT&T store and they held it up side by side with other 3G phones they had full signal in 3G but the iphone 3g had 1 bar. This seems like strong evidence its the phone to me. If I turn 3G off its fine but what is the point in having a 3G phone. Apple support finally told me to take it to an Apple store but there is more than a 24hr wait to get an appointment. Of course I tried to just go in and the person I talked to turned 3G back on(since I left it off so I could actually get calls) and of course in the apple store in Cherry creek there is full signal. Unfortunately I don't live or work there.

Does Apple make different iPhones for T-Mobile and ATT?

Here is the question, Will a T-Mobile phone have fewer dropped calls than an ATT phone under similar conditions, Both iPhones each having a T-Mobile simm card in each? The ATT iphone was a 4s and the proposed T-Mobile iPhone 6 plus.
Here is our story, In May 2014 , we moved to the metro Denver/Boulder area we arrived with iPhones 4.S purchased from ATT but had switched service to T-Mobile before our move. The cell phone service was unsatisfactory with a number of dropped calls. so we switched to iPhone 5s from Verizon .
Now we are interested in buying a iPhone 6 plus each for me and my wife so we are considering a T-Mobile iPhone 6 plus because of their deals however, I am suspicious of their service.
Today I went to the T-Mobile store and relayed our experience with the ATT phones/T-Mobile simm cards. They assured me that the problem was with the ATT phones and not with T-Mobiles service.
1.Is this accurate?
2.Would you stick with Verizon?

swifty8 wrote:
1.Is this accurate?
No, it's utter nonsense.
AT&T and Verizon tend to be more expensive than Sprint or TMobile. Sometimes, you get what you pay for.

Multiple issues with PCI-5640R FPGA: DAC and Strange Execution at Host

We are working on a communications systems project using the PCI-5640R
IF-RIO transceiver and the FPGA module. At the FPGA, a sequence of bits are
being modulated through multiplication with the sine wave generator. The
next step is to take the modulated sinusoidal signal and send it through the
DAC. Throughout this project, we have been using the Analog Input and Output
example project from Getting Started with the 5640-R IF... as a template
to build this project. There are, however, several issues/questions we
have. Attached are the HOST and FPGA vis that we are working with.
1. The host only runs every other time. At the host (BPSK_TX(HOST).VI, the execution gets
halted for an infinite period of time at one of the FIFOs until 'stop' is
hit. But then at the subsequent execution, the host completes execution
of the program. In other words, the host is only receiving data from the
FPGA every second time it is run. Why is this happening? Are we missing
something at the host or FPGA VI?
2. How exactly do we send our own digitized signal through
the DAC? As seen in one of the FPGA VIs, we have tried modfiying the
output section of the FPGA VI in the Analog Input and Output project in which
the FPGA reads from the FIFO. In our case, we are modulating the signal
in a separate section, writing it to a target-scoped FIFO and then reading from
that FIFO and processing the data as in the example. This modified FPGA
vi is "BPSK_TX(FPGA).VI)
Unfotunately, we are not observing anything at an oscilloscope
connected to the transceiver. Even when we try to pass in a
"custom" signal at the HOST we have no luck observing anything
coherent. As seen in the bare_sine_wave_test (FPGA).vi, we have
attempted a relatively simple way of sending a signal through the DAC, yet
still no luck. I am guessing that this is related to issue #1.
On a related note, when
receiving the signal and running it through the ADC, what steps are
necessary? Can one assume that it is
similar to the FPGA.VI in the analog input and output example?
3. How do for loops and while loops synchronize with timed loops
and frames in the FPGA? In the FPGA we are using a for loop to
modulate the signal because the sine wave generator cannot be contained within
a timed loop on the FPGA. This will be important to us because at the
receiver we will need to know the symbol rate in order to recover the signal.
I would sincerely appreciate any feedback or help that can be provided
on this,
Attachments:
BPSK_TX(FPGA).vi ‏152 KB
BPSK_TX(HOST).vi ‏257 KB
bare_sine_wave_test (HOST).vi ‏135 KB

It may be that the FPGA Refernce has not been binded. The issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control. This is an option on the popup menu when clicking on the Open FPGA VI Reference VI. In some cases, it may already be selected in the popup menu. In this case, unselect the Bind to Typedef option. For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option. In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI. In some cases, I have to Save All, close the host VI and all subVIs. Then reopen the host VI. This has always working in all cases for me.
Jerry

Error code 63003..while running a FPGA prog on Host PC using FPGA reference VI

Hi,
when i run my FPGA program on HOST PC using a FPGA reference vi on windows platform, I get an error code 63003 (FPGA bit file out of date). When I go back, recompile and run the FPGA program on the FPGA target, then shut it and come back to HOST PC and run my application with FRGA Open refence vi, it runs with out any error! Does any one know why I get that error code 63003

This error means that the VI which is downloaded to the FPGA was changed on the host/development system, but has not been recompiled. By recompiling it you resolve this problem.
When a LabVIEW FPGA VI is compiled for the FPGA, the bit stream, which will be downloaded to the FPGA, is stored in the VI file. When LabVIEW RT or LabVIEW Windows attempts to download the bit stream to the RIO card, it makes sure the bit stream corresponds to the VI source code in the same file. This is necessary so that the host application can properly communicate with the VI on the FPGA. If the two are not the same, this error is generated from the Open FPGA VI Reference function in the host application.
Christian L
NI Consulting Services
Christian Loew, CLA
Principal Systems Engineer, National Instruments
Please tip your answer providers with kudos.
Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
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Where to find FPGA trim report of the compiler

I have problem when compiling my FPGA VI for cRIO 9101.
It seems that some of my signal is trimmed, but I can not find the trim report.
Also, I don't know what kind of problem in VI may generate this issue. My original VI was OK under LV 8.0 (FPGA). But I got Slices overloading (108%) under LV 8.20. After changing several front panel clusters into constant values, I reduced the slices to 90%, and nothing else is used more than 80%. However is still have this problem.
The error message is here:
++++++++++++++++++++++++++++
Using target part "2v1000fg456-4".
Mapping design into LUTs...
ERROR:MapLib:661 - LUT3 symbol
   "mytop/n_898/resVI/n_676/n_673/n_662/n_651/n_645/_n00051" (output
   signal=mytop/n_898/resVI/n_676/n_673/n_662/n_651/n_645/_n0005) has input
   signal "mytop/n_898/resVI/n_676/n_673/n_662/n_651/eo00000cbc" which will be
   trimmed. See the trim report for details about why the input signal will
   become undriven.
ERROR:MapLib:661 - LUT3 symbol
   "mytop/n_898/resVI/n_676/n_673/n_662/n_651/n_645/_n00051" (output
   signal=mytop/n_898/resVI/n_676/n_673/n_662/n_651/n_645/_n0005) has input
   signal "mytop/n_898/resVI/n_676/n_673/n_662/n_651/eo00000ba0" which will be
   trimmed. See the trim report for details about why the input signal will
   become undriven.
Error found in mapping process, exiting...
+++++++++++++++++++++++++++++++++++++++++

For the most part you will get a broken arrow when you have unsupported datatypes in FPGA. The saturation functions are an exception. In general, when things are correctly installed the saturation VI is really just a placeholder for the FPGA code that will need to be created for it. However, you can run the VI in emulation mode and therefore we need to define the behavior of the code for emulation mode. This behavioral code is what uses floating point numbers that you see on the block diagram of the function. We do not check for unsupported types in NI functions, because we expect them for emulation. When emulation is off and you run the VI we see that the saturation function is there and generate special functional code. However, if the VI is saved in a version without FPGA this flag is removed and we no longer generate special code for the function, but rather just generate code for the diagram the way it is (floating point and all). I have filed a CAR to the developers in order for them to catch this error earlier in the process and provide a cleaner error message.
Regards,
Joseph D.
National Instruments

Erasing Flash Memory of Spartan 3E FPGA

Hello,
I'm programming a Spartan 3E FPGA, and I believe there are a few VIs left in the flash memory from the previous user of the board. I'd like to just clear out the flash memory. 've been playing around and can't seem to find how to clear it through LabView on a spartan.
I've already had a look at this.
http://digital.ni.com/public.nsf/allkb/4789525480C3B78C8625714000746BFD\
It should be pretty simple, anyone know how to go about it?
thanks in advance!

Are you referring to the platform flash (XCF04, this can be used to automatically-configure the FPGA on powerup) or the Strataflash (which cannot easily be configured to do so, but can be used for persistent storage)?
If it's the former, I would suggest using iMPACT to clear the flash part. For the later, there are a few examples that interact with the Strataflash, that's as good a starting point as any.

FPGA code only works on alternate executions

Hi,
I have some code I wrote for FPGA which, by itself, works fine. I tried to use "Open FPGA VI Reference" as part of a previous (non-FPGA based) VI. However, I find that the full code only works on alternate executions. I thought this may be because the FPGA VI is not being reset properly. However, I have used "Close FPGA VI Reference" and chose "Close and Reset" and the problem remains.
Any help is appreciated,
Thanks.

Hi Gary,
I hope you are doing well today! What version of LabVIEW FPGA are you using? When you say you are doing 'alternate executions', what exactly do you mean? Do you run your host VI, stop it and then run it again? Have you tried just using Close instead of resetting the FPGA VI? Also, what are you using the reference for? What are you invoking? It would, also, be better if you post a screenshot of your VI.
Adnan Zafar
Certified LabVIEW Architect
Coleman Technologies

FPGA Read/Write Control Issues

Hello all! Rather new to using FPGA, but I have an interesting issue that's popping up.
Currently pulling in RAW voltage data from a set of sensors (Pressure Transducers, Load Cells, etc) through a cRIO DAQ. Have the FPGA file setup to pull in that data already and have the main VI and all the sub-VIs working just fine.
What I'm trying to do is save the raw voltage data (TDMS files) on the lower level and the convert and display on the upper level so that I don't have to convert and save (speed up saving data). So that leaves 3 distinct levels/sections:
On FPGA that pulls in the raw data
On FPGA that saves the raw data
Main VI that does all the controls/conversions/displays etc.
Number two is where I'm having an issue. I want to save all the data in parallel so I'm creating a save FPGA for each I/O device (8 Relays to command solenoid valves, 3 Pressure Transducers, 1 Load Cell, 4 Thermocouples). To do this I want to create a separate VI for each device (not sure if that's a smart thing to do).
The issue I'm having is when I use the FPGA Read/Write control to read in from the Target and save to the TDMS. When I only use a single FPGA target reference the lines are broken, but as soon as I switch to two targets, it now works.
Any reason why it might be doing this? Any ideas/suggestions at all on how to go about setting this up in general?
Thanks!

Hi,
HySoR wrote:
The issue I'm having is when I use the FPGA Read/Write control to read in from the Target and save to the TDMS. When I only use a single FPGA target reference the lines are broken, but as soon as I switch to two targets, it now works.
Could you take a screenshot and post this part of your code? I'm having trouble understanding what you are describing.
Craig H. | CLA | Systems Engineer | National Instruments

Sub contractor employees

Hello,
I know this question has come many times but still I want clarification.
We need to assign subcontractors to PM work center and maintain their schedule so that we can do the scheduling.
Please help how to do this without creating them as employees.
Regards,
Smart

Hi Smart,
In case if you have 5 sub contractors and you need to create a work centre with No of capacity has 5, if they work for 8 hours, then the total capacity available is 40 hrs.
On assigning this to order, you will be able to identify whether the capacity is exceeded or not.
Also i am not sure, what you mean by sub-contractor wise (if there are no persons assigned to work centre HRMS), by which way you are trying to achieve scheduling.
So you can wait for other experts to get your solution.
Regards
Terence

Streaming Data between Smart Camera and FPGA?

Is there a way I can stream data between a smart camera (NI 1774) and a FlexRIO FPGA module (PXIe-7961R)? I understand that data from the smart camera can only come from a USB or an Ethernet connection, I intend to plug the camera to the PXI controller (PXIe-8135), the chassis I'm using is PXIe-1082 so the p2p data transfer at 8GB/s should be possible between the controller and the FPGA module.
As a note: The processing I'm trying to do is too computationally intensive so its not possible to do it on the smart camera itself.

Hi faisalm88,
This is Emi from NI.
Unfortunately there is no direct streaming between smart camera and FlexRIO FPGA.
(It has to be smart camera -> controller --> FlexRIO FPGA board)
And thus I have a few suggestion for you.
If you can tell me what's your application (does it have to be smart camera? Is the "data" you are talking about image?) ,
I might can come up with even better solution.
1. Do not use smart camera.
The iamge quality of 1774 can be easily replaced with USB web cam.
You can connect the web cam to your PXI controller and transfer data to your FPGA board.
If you are using LabVIEW 2014 and newer, there is function to transfer image data to FPGA.
2. Do not use 8135
Assuming if you are using FlexRIO just to enhance image processing performance,
then if might be better to use CVS
http://sine.ni.com/nips/cds/view/p/lang/ja/nid/212667
It has both FPGA and quadcore processor.
3. Stream image data&colon; 1774 --> 8135 --> 7961R
Let me know what method you want to take
and I can describe them more in detail.
Emi
Emi Nakayama
Applications Engineer, Japan
National Instruments

FPGA Read/Write Control Function Issues

Hello all! Rather new to using FPGA, but I have an interesting issue that's popping up.
Currently pulling in RAW voltage data from a set of sensors (Pressure Transducers, Load Cells, etc) through a cRIO DAQ. Have the FPGA file setup to pull in that data already and have the main VI and all the sub-VIs working just fine.
What I'm trying to do is save the raw voltage data (TDMS files) on the lower level and the convert and display on the upper level so that I don't have to convert and save (speed up saving data). So that leaves 3 distinct "levels/sections":
On FPGA that pulls in the raw data
On FPGA that saves the raw data
Main VI that does all the controls/conversions/displays etc.
Number two is where I'm having an issue. I want to save all the data in parallel so I'm creating a save FPGA for the I/O devices (8 Relays to command solenoid valves, 3 Pressure Transducers, 1 Load Cell, 4 Thermocouples).
The issue I'm having is when I use the FPGA Read/Write control to read in from the Target and save to the TDMS. When I only use a single FPGA target reference the lines are broken, but as soon as I switch to two targets, it now works.
I've attached a screen cap of the current problem. The set-up on the bottom (with only one target) doesn't work. But the second I add more than one target, it works.
Any reason why it might be doing this? Any ideas/suggestions at all on how to go about setting this up in general?
Thanks!
Attachments:
FPGAError.jpg ‏35 KB

HySoR,
You might check the documentation for "data" terminal of "TDMS Write" (http://zone.ni.com/reference/en-XX/help/371361H-01/glang/tdms_file_write/). One DBL element is not accepted, but 1D DBL array is accepted.
data is the data to write to the.tdmsfile. This input accepts the following data types:
Analog waveform or a 1D array of analog waveforms
Digital waveform
Digital table
Dynamic data
1D or 2D array of:
Signed or unsigned integers
Floating-point numbers
Timestamps
Booleans
Alphanumeric strings that do not contain null characters

RT & FPGA Modules – I am missing a fundamental concept

Recently I have been asked to program a compactRIO 9074 and in the midst of researching how to do that, I have become thoroughly confused…
I understand that the RT module is used for precise timing (i.e low jitter) and somehow it interfaces with the host computer (i.e. computer with the VI). I also understand the FPGA module allows you to, and forgive the simplicity, recreate the circuit on the chip, thus allowing virtually true multithreading and really fast speeds. Also, the FPGA interacts with the IO modules/ports.
The thing that I am unclear about is:
When you program the compactRIO 9074, do you select only one module (RT, FPGA) and ignore the other?
-or-
Do you use both modules - the RT module for the embedded hardware and the FPGA module for the FPGA bitstream? If so, how does the embedded hardware talk to the FPGA? Is this something you have to manually program? Any literature/tutorials on this?
-or-
I’ve even read something to the effect- the embedded module gets programmed with the RT module when the cRIO boots up for the first time. If that’s true, then does RT module get used only that only time and all programming thereafter is done with the FPGA module? Is the one-time RT module provided by NI or is this something I would have to create?
I think that I am missing something so fundamentally simple that this whole project is becoming so unnecessarily complicated.
Thanks in advance for the help.
Joe T.

It is a bit complicated, but powerful and flexible. If your needs are simple, NI provides tools (such as the scan engine) so you may not need to get into all the details.
The cRIO is almost a full computer, running a dedicated, real-time operating system (either PharLap ETS or VxWorks, depending on your cRIO). On top of that, there's the LabVIEW runtime. That computer also contains an FPGA, similar to if you bought one of the NI PCI FPGA cards and installed it in your PC.
The FPGA talks to the processor in the cRIO. If you need full control over the FPGA, then you write that code yourself and use DMA FIFOs and front-panel controls to transfer data between the cRIO and FPGA. If you just need access to the IO, you can use the Scan Engine, as previously noted. You also need a way for the cRIO to talk to your computer. Again, you can write code yourself, or use the NI-provided tools such as network shared variables. If you don't need the cRIO to do anything other than act as an expensive data acquisition device, you can link a shared variable to an I/O channel and access it directly from your PC, or share your IO variables over the network. Run a search on the NI site for "network shared variable scan engine" for more information.
You write separate code for the cRIO and the FPGA. You can run your VIs on the cRIO within the LabVIEW development environment and use most of the standard debugging tools, it will just be a bit slower to respond than when the LabVIEW code runs on your PC. When you have a working program, you can build an application and deploy it to the cRIO so that it will run at startup. You can do this as many times as you like. The LabVIEW program on the cRIO may contain an FPGA bitstream embedded in it. Writing code for the FPGA is more complicated - there are limitations, and you must compile the code before you can run it (no interactive debugging unless it's running in simulation).

FPGA Contractor in Denver/Boulder Area

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