Multiple issues with PCI-5640R FPGA: DAC and Strange Execution at Host

Question

We are working on a communications systems project using the PCI-5640R
IF-RIO transceiver and the FPGA module. At the FPGA, a sequence of bits are
being modulated through multiplication with the sine wave generator.  The
next step is to take the modulated sinusoidal signal and send it through the
DAC. Throughout this project, we have been using the Analog Input and Output
example project from Getting Started with the 5640-R IF... as a template
to build this project.  There are, however, several issues/questions we
have.  Attached are the HOST and FPGA vis that we are working with.  
1.  The host only runs every other time.  At the host (BPSK_TX(HOST).VI, the execution gets
halted for an infinite period of time at one of the FIFOs until 'stop' is
hit.  But then at the subsequent execution, the host completes execution
of the program.  In other words, the host is only receiving data from the
FPGA every second time it is run. Why is this happening?  Are we missing
something at the host or FPGA VI?  
 2.  How exactly do we send our own digitized signal through
the DAC?  As seen in one of the FPGA VIs, we have tried modfiying the
output section of the FPGA VI in the Analog Input and Output project in which
the FPGA reads from the FIFO.  In our case, we are modulating the signal
in a separate section, writing it to a target-scoped FIFO and then reading from
that FIFO and processing the data as in the example.  This modified FPGA
vi is "BPSK_TX(FPGA).VI)
Unfotunately, we are not observing anything at an oscilloscope
connected to the transceiver.  Even when we try to pass in a
"custom" signal at the HOST we have no luck observing anything
coherent.   As seen in the bare_sine_wave_test (FPGA).vi, we have
attempted a relatively simple way of sending a signal through the DAC, yet
still no luck.  I am guessing that this is related to issue #1.  
On a related note, when
receiving the signal and running it through the ADC, what steps are
necessary?  Can one assume that it is
similar to the FPGA.VI in the analog input and output example? 
3.  How do for loops and while loops synchronize with timed loops
and frames in the FPGA?  In the FPGA we are using a for loop to
modulate the signal because the sine wave generator cannot be contained within
a timed loop on the FPGA.  This will be important to us because at the
receiver we will need to know the symbol rate in order to recover the signal.
 I would sincerely appreciate any feedback or help that can be provided
on this,
Attachments:
BPSK_TX(FPGA).vi ‏152 KB
BPSK_TX(HOST).vi ‏257 KB
bare_sine_wave_test (HOST).vi ‏135 KB

Answer 1

It may be that the FPGA Refernce has not been binded.  The issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control.  This is an option on the popup menu when clicking on the Open FPGA VI Reference VI.  In some cases, it may already be selected in the popup menu.  In this case, unselect the Bind to Typedef option.  For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option.  In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI.  In some cases, I have to Save All, close the host VI and all subVIs.  Then reopen the host VI.  This has always working in all cases for me. 
Jerry