Hardware timed Dataacquis​ition with cRIO

hi,
i am trying to develop a code for dataacquisition using cRIO. my application specifications are:
Digital Input: 1 (trigger for acquisition, i have a cRIO-9401 DIO module
Analog Inputs-2 (i have cRIO-9215 and also cRIO-9221 AI modules for this)
i need to develop  a code in which the acquisition is triggered by a pulse signal of Period=20 ms and On-time=1 ms on a falling edge
the two analog inputs are: a current waveform which is on when ever there is a trigger and shuts-off on the falling edge

Hello,
By running the VI for a second time, you mean, stop the whole Host VI and the re run it? Or just trigger it for the second time? When you say that it reduced, you mean in Amplitude or the number of samples? I ask this because you have "Data read" that once you write a True to it, it will always be true.  You never set it back to False, so the FPGA keeps running all the time, overwriting the "AI Data",
Ricardo S.
National Instruments

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