HLS creates internal clock enable??

Question

In HLS (2015.2), I created a simple comparator circuit. The HLS C-simulation worked fine.
The HLS C-function compares 8-bit integers received from an 8-bit data bus against a fixed array
of 8-bit integers. If the first integer matches, a counter is incremented, and the C-function
will then look for the 2nd integer in the array. If the sequence of 8-bit integers on the data
bus matches the sequence of bytes in the stored array (distributed memory Eg. ROM), a  match
is detected.
After observing a good C-simulation, I then instantiated the HLS Verilog file code into the actual
hardware, and attempted a Modelsim simulation. It did not work!! This is a very simple circuit. The
Verilog file has the ports below.
ap_clk
ap_rst
ap_start
ch(7:0)   <---    This is the incoming 8-bit data bus.
ch_valid
ap_return   <---   This is the match signal.
If ch_valid is HIGH, the comparator should compare ch(7:0), against the known internal fixed array of 8-bit
integers. The signal ch(7:0) changes every ap_clk. The problem with the hardware is that HLS
created an internal clock enable. For this circuit to work, the ch(7:0) bus needs to be stable for
2-clock cycles. The only reason I found this was because saw what was happening in ModelSim.
When coding in C, there is no concept of clock. I thought HLS was intended to allow the user to create
code and to not be concerned with clocks and other hardware events.
Questions:
1. Is the purpose of HLS to allow a software programmer to be able code and create hardware, or does an HLS
programmer need a hardware background?
2. If the HLS programmer does not need a hardware background, how would a software programmer find
an internal clock enable?
3. Is there a switch to prevent HLS from creating code that uses internal clock enables, or does the C-code
need to written in a certain way?
Thanks!

Answer 1

In HLS (2015.2), I created a simple comparator circuit. The HLS C-simulation worked fine.
The HLS C-function compares 8-bit integers received from an 8-bit data bus against a fixed array
of 8-bit integers. If the first integer matches, a counter is incremented, and the C-function
will then look for the 2nd integer in the array. If the sequence of 8-bit integers on the data
bus matches the sequence of bytes in the stored array (distributed memory Eg. ROM), a  match
is detected.
After observing a good C-simulation, I then instantiated the HLS Verilog file code into the actual
hardware, and attempted a Modelsim simulation. It did not work!! This is a very simple circuit. The
Verilog file has the ports below.
ap_clk
ap_rst
ap_start
ch(7:0)   <---    This is the incoming 8-bit data bus.
ch_valid
ap_return   <---   This is the match signal.
If ch_valid is HIGH, the comparator should compare ch(7:0), against the known internal fixed array of 8-bit
integers. The signal ch(7:0) changes every ap_clk. The problem with the hardware is that HLS
created an internal clock enable. For this circuit to work, the ch(7:0) bus needs to be stable for
2-clock cycles. The only reason I found this was because saw what was happening in ModelSim.
When coding in C, there is no concept of clock. I thought HLS was intended to allow the user to create
code and to not be concerned with clocks and other hardware events.
Questions:
1. Is the purpose of HLS to allow a software programmer to be able code and create hardware, or does an HLS
programmer need a hardware background?
2. If the HLS programmer does not need a hardware background, how would a software programmer find
an internal clock enable?
3. Is there a switch to prevent HLS from creating code that uses internal clock enables, or does the C-code
need to written in a certain way?
Thanks!