How do I calculate the CAN arbitration ID right?

Hello Again!
From my partner firm I got a scheme to calculate the extended arbitration ID. The bits are devided like this:
- 6 bit 5bit 1bit  3bit   4bit  5bit  5bit
The values got to be in decimal:
- 32-31-0-1-0-0-1
I figured out the following arbit.ID in Hex, but it seems to be wrong:
107C4001
This happend with the attached ID.
Whts wrong?
Attachments:
calc_arbitID.vi ‏26 KB

I tried to analyze your trace, but I don't see how it can be correct. Here is what I would expect to see (now, I could be wrong, but this is based on my calculations)
With your original ArbID of : 107C4001
SOF              29-bit ARB ID
 0    1 0000 0111 1100 0100 0000 0000 0001
But, the 29-bit protocol states that you send the 1st 11-bits followed by SRR and IDE (both recessive)     
SOF  1st 11-bits    SRR IDE   Remaining 18-bits
0    100 0001 1111   1      1    00 0100 0000 0000 0001
But, we need to account for bitstuffing (5 consecutive identical values results in an additional bit, deliniated with a ^ under it in my image),
so I would expect to see the following on a scope:
SOF  1st 11-bits      SRR IDE   Remaining 18-bits
0    100 00011 11101   1   1    00 0100 00010 0000 10001
            ^     ^                        ^       ^
What you saw was:
1011 1110 0000 1000 1101 1111 0111 1101 1111 0011 0111 0001 0101 0010 0001
<< Remove Bitstuffing >>
1011 111  0000  000 1101 1111  111 11 1 1111  011 0111 0001 0101 0010 0001
<< Compress, Assume you skipped the SOF and sent a 29-bit arb id >>
101 1111 0000    0   0   0 1101 1111  111 11 1 1111  011 0111 0001 0101 0010 0001
 1st 11 bits    SRR IDE   
SRR and IDE are both dominate, which violates the CAN spec for a 29-bit id. This could be an 11-bit ID, which would have SRR and IDE both dominate to send a data frame. However, afterwards you have r0 and DLC which should be recessive and <=8 respectively, which are really dominate and 13.
<< Compress, Assume you skipped the SOF and sent a 29-bit arb id >>
101 1111 0000    0   0   0 1101 1111  111 11 1 1111  011 0111 0001 0101 0010 0001
 1st 11 bits    SRR IDE  r0  DLC
So, I think you have either misinterpreted the scope or did not capture the entire transfer.

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