How do I know what is the host-side FIFO depth?

Question

Hi.
In LabVIEW FPGA, the FIFO.Configure Method lets you determine the depth of the FIFO on the <u>host</u> side.
If my VIs have never included this method, is there a way of knowing how deep this FIFO has been all along?
I set my FPGA-side FIFO to be 8k deep.  What depth does the host-side FIFO default to?
I am asking because I am getting some failures in my test VI that uses FIFOs and I suspect overflows are to blame.
Thanks,
AlejandroZ
Solved!
Go to Solution.

Answer 1

Here is a copy+paste from a post I made back in May 2010.  I'll add some tags to the original so it should facilitate easier searching.
The DMA FIFO is actually implemented in 2 parts, you define the FPGA size in the project explorer(actual FPGA fabric), the Host side is defined programatically (Host RAM).
There is a configure method you can run on the Host, the default for the Host side is 10,000 elements.  I would set the FPGA side much smaller, 1000 or so elements, save a lot of FPGA fabric.  Configure the Host side to 64,000 or something.
Here is a help link to the Configure method:
http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgahost/fpga_method_fifo_config/
and a link to the DMA FIFO help:
http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgaconcepts/pfi_data_transfer/#DMA_FIFOs