How to add DRAM FIFO-128bi​t to the FPGA project?
How do I add the DRAM FIFO - 128 Bit Memory Interface to a PXIe-796XR RIO module?
Above project is from one of the example projects. I know how to add DRAM but not how to configure it as FIFO 128bit as above.
Any guidance is appreciated.
Solved!
Go to Solution.
I really have not found a way to add the DRAM 128bit fifo to the design. Adding normal DRAM and target specific FIFO's and host-target FIFO's is easy, but the special DRAM implemented as a giant FIFO I could not find how to add. And I have searched the documentation - but obviously missed the key point. I use labVIEW 2013. Any hints are appreciated.
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