How to affect the actual FPGA clock rate?

Question

Hallo,
I developed a FPGA-VI, which should run with 80 MHz clock rate on the PCI 7833R board.
This was no problem at the beginning, but meanwhile the code got bigger (Slices: 30%). Now the compiler says that there is an error with the timing constraints. The maximum clock it can reach is 74 MHz.
Unfortunately I need the 80 Mhz to be fast enough.
What parts of the code influence the actual clock rate?
How can I get it faster?

Answer 1

I think you missunderstood what I mean:
The problem is not how many ticks a while loop needs for one cycle.
The problem is the clock rate setting for the FPGA-board. It is set to 80 MHz and not the Default 40 MHz.
When I compile my VI the compiler reports that it can't keep the 80 MHz. That means for example that a Single Cycled Timed Loop doesn't need 12.5 ns but for instance 13.4 ns.
If I separate my code in 2 parts and compile each part as a separate project, the compiler can keep the 80 MHz. Only together it doesn't work.
So the whole problem has something to do with the size of the project, the depth of the structures etc.
So I need to know for example what structures slow down the clock most, or something like that.