How to use a pll output to drive the clock input?

when i use the following code to generate a clock（CLK00IN) from MHZIN to drive the normal logic,it work normally,but when i use it to drive the gtp clock input port CLK00,CLK00IN become 0 (no signal),why?
IBUFG system_clk_ibufg
.O                              (sys_tile0_gtpclkout0_0_to_cmt_i),
.I                              (MHZIN)
PLL_BASE #
         .CLKFBOUT_MULT     (10),
         .DIVCLK_DIVIDE     (1),
         .CLK_FEEDBACK      ("CLKFBOUT"),
         .CLKFBOUT_PHASE    (0),
         .COMPENSATION      ("SYSTEM_SYNCHRONOUS"),
         .CLKIN_PERIOD     (25.0),
         .CLKOUT0_DIVIDE    (5),
         .CLKOUT0_PHASE     (0)
    system_clk_pll
         .CLKIN             (sys_tile0_gtpclkout0_0_to_cmt_i),
         .CLKFBIN           (CLK00FB),
         .CLKOUT0           (CLK00OUT),
         .CLKOUT1           (),
         .CLKOUT2           (),
         .CLKOUT3           (),
         .CLKOUT4           (),
         .CLKOUT5           (),
         .CLKFBOUT          (CLK00FB),
         .LOCKED            (),
         .RST               (system_clk_pll_reset_i)
    BUFG sys_clkout0_bufg_i
        .O              (CLK00IN),
        .I              (CLK00OUT)
    );

Whether this experiment is done for test purposes?
GT should not have any impact on CLK00IN signal in the code here. GT comes into picture after sys_clkout0_bufg_i. Please check if any optimization happened during implementation.

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