Information from opensparc package, don't reply,thanks.

Question

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verification:
i find sims script use tools\src\sims\sims,1.262 script and one of the two config file (core1 and chip8) to realize the simulation.
Differences between core1.config and chip8.config are:
1. the switch "-config_rtl". In core1.config,there is one RTL_SPARC instance while eight in chip8.config.
2.the switch "-config_rtl".In chip8.config, there is oneRTL_IOBDG instance.
3.the switch"-sas_run_args=-DSP".In core1.config, there is one while 8 in chip8.config.
4. the switch "-sim_run_args=+BW_BFM".In core1.config,there are 7 bfm which none in chip8.config.
5. other differences.
synthesis
1.tools\perlmod\rsyn,1.0 is the true script;
2.design\sys\synopsys\script\target_lib.scr should be changed to use your own asic library;
3.design\sys\synopsys\block.list is don't touch module list. OpenSPARCT1_DVGuide.pdf would make a mistake about block.list

Answer 1

Due to some reason, I can't continue doing verification.I am now trying to read HDL code and to understand the structure.
Now modules under analog directory will be analyzed first.
Under this directory there are the funcional view of the analog blocks in Osparc T1.
1.under dir-"analog\bw_clk",there are the modules which gives the description of clocks.there are jbus_clk,ddr_clk,cmp_gclk.
The module"bw_clk_cclk_hdr_48x" is unuseful.
The module "bw_clk_cclk_scanlasr_2x" defines the scan data out(so).
The module "bw_clk_cclk_sync"defines the synchronization of the jbus data transferring(tx and rx) and dram data transferring by cmp_clk.
The module "bw_clk_gl" defines the global clocks and buffers.
The module "bw_clk_gl_rstce_rtl" defines the global clock buffers and repeaters.
2.under dir-"bw_ctu_pad_cluster",there is only one file.One signal is jclk(J_CLK) and will be enable when define the RTL_PAD_CTU(RTL_CTU) state.Another signal is tsr_testio(TSR_TESTIO[1:0]) which is from tempsensor.
Also 1.5v digital vdd and 1.8v analog vdd are defined.
3.under dir-"bw_iodll", there are three files.
One is bw_iodll.v, which is master delay-locked loop.the signal lpf_out will be bypass_data if io_dll_bypass_l equals to zero.
The second is bw_ioslave_dl.v, which is slave delay line module.The signal dqs_out will ouput after the input has delayed 1/4 cycle.
The third is bw_iodll_code_adjust.v.Because I have no idea about PLL. So i don't understand about it.
These three files are not used by the top module IOP,which sounds strange.
4. under dir-"bw_pll",there is only one file- bw_pll.v,which describe the functional view of PLL.It seems PLL uses 200MHZ clock input. I don't understand about it.
5.under dir-"bw_rng",there is one file. this is the random number generator module.the random number is generated per 0.5 us.the rng_clk is 1us period.
6.under dir-"bw_temp_diode",there is one file,which is temperature senser diode module with three pins.(I don't know how does it work)
7.under dir-"bw_tsr",there is one file,which is temperature sensor register.dout is the weighted value of temperature.
p.s. I will post my idea about opensparc T1 in following days.Because I am now a student and busy for my lessons , I would make many mistakes .Hope everybody give me wise advices in new posts.
Thanks.