IODELAY2 as variable output using partial reconfiguration

Question

Dear all,
we want to use the IODELAY2 primitive as a variable output delay, which is not really foreseen by Xilinx. The workaround, which is shown in AR34276, does not really work for us, as the signal integrity is not good enough. So we had the idea of configuring it to a fixed output delay and use partial reconfiguration to change the delay. This is in principle working fine (we got about 35 ps/step as delay), but we have observed strange side effects, like Chipscope seems to be broken or parts of the firmware do not work properly anymore, after applying the bit files via the ICAP interface.
We generate the partial bitfiles from the netlist after P&R by changing the delay value in FPGA editor. From the new netlist and the original bit-file we can get the partial bitfile:
bitgen -d -w -g ActiveReconfig:Yes -g CRC:Disable new.ncd -r original.bit part.bit
Can someone help me sorting out, what's going wrong?
Cheers
Marius

Answer 1

Marius,
When you over-write a frame of configuration logic, it may affect the existing design adversely.  Allowing partitions of a reconfigurable design to not be affected by a reconfiguration is a difficult task.  One frame is just one of more than twenty frames required to change a sinlge CLB/interconnect tile.  IODELAY2 is no different, it is many frames wide, and thoise frames share data with other tiles.
If possible, it is best to stop the existing design, reconfigure, and then restart.  At a minimum, the reconfigurable section of the design must be stopped, isolated, re-written, and then restarted (enabled).  In the PR flow, a zeroing out partial bistream is loaded inbetween the two reconfigurable partitions to clear  completely the reconfigurable partition.