IP integration Node: failed to link the design

I'm unable to generate supporting files when importing a VHDL file into IP integration node. I have seen people having the same issue because they used an unsupported OS but my OS is supported by Vivado 2014.4.
I have:
NI LabView 2014 with all the modules and latest updates installed
Xilinx Vivado 2014.4
Windows 8.1 64 bit (which is sipported by labview)
I get the following error:
Waiting for 2 sub-compilation(s) to finish...
ERROR: [XSIM 43-3238] Failed to link the design.
Generated IP unsuccessfully. Your source file(s) can't work for the FPGA famili(es) you select. Fix the above error(s) or warning(s) and generate the IP again, or go back to previous page to reselect FPGA Family Support.
It is worth to mention that I have selected only one FPGA family (zenq) which vivado supports. The code that I'm importing is correct and very short. Just a LED test which worked fine on simulations. What is causing this issue and how my I solve this?
Solved!
Go to Solution.

Hi aan928
You are correct in that 8.1 does support LV 2014 but LV2014 isn't FULLY supported (as in modules and drivers) FPGA being one of them. The Compiler tools that we are dependent on Xillinx for unfortunatly aren't at this moment in time. Although some FPGA compilation may work, not all compilations will. Unfortunatly there is no timeline in terms of how Xillinx & NI will fully implement support for specific modules with window 8.0 & 8.1.
Please reference the document below to see a full list of compatabilities beween NI tools & 8.0 which may provide some help
http://www.ni.com/white-paper/14281/en/
Regards
J
J Hird CLAD
NI UK Applications Engineer

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http://technet.oracle.com
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: : Oracle XML Team
: : http://technet.oracle.com
: : Oracle Technology Network
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: : : Mike
null

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>
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>
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>
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