ISE issues based on versions and FIR filters

Question

Hi:
I am using Xilinx ISE 14.7 version and generated two port RAMS for Spartan 6 FPGA in VHDL.   When I generate my two port RAM, the RAM generated a signal called”Wea” with the type of STD_LOGIC_VECTOR (0 downto 0). My present VHDL signal type is STD_LOGIC which is connecting the this pin in the port map. So I have some type error when I compile. I try to change the type to STD_LOGIC in the generated RAM code, but I could remove the errors in type because the *. ngc file is made for STD_LOGIC VECTOR and not allow me to change to STD_LOGIC. Please give me any suggestion to my problem as soon as possible. I am struggling with this error more than two weeks now. It is kind of rotating.
The ideal solution would be, if I can set “wea” pin with a bit, but I have not found the way of doing this in COREGEN. Please suggest
I also have another question. Have anyone used the FIR compiler to generate FIR filter? Can I use this along with C code or VHDL code? How do I use this to customize my FIR filter?
the sooner you reply the better would be?
Thanks
Hari

Answer 1

Hi Hari,
So you basically need to connect a std_logic signal to a port of type std_logic_vector(0 downto 0), is that right?
How about
std_logic_vector(0) <= std_logic
I also have another question. Have anyone used the FIR compiler to generate FIR filter? Can I use this along with C code or VHDL code? How do I use this to customize my FIR filter?
Yes, many many people use the FIR compiler. It's an IP core, so it will be delivered from coregen as a NGC netlist with a VHDL or verilog wrapper. It's not software; it's hardware.
How exactly do you want to customize it? The core provides you with a ton of options including specifying different coefficients, reloading them, different architectures, etc. Make sure to read the doc for it and play with it in the GUI to get an idea.