MIG : K7 - DDR3 - 1600 MHz - IBIS Model for addr/cmd with VccAux = 2.0V

Question

Hi everybody !
I have a problem in the generation of my IBIS file...
I'm using Vivado 2015.1 and MIG v2.3. My FPGA is xc7k325tffg900-2.
In the xdc file (generated by the MIG), I have this type of constraint for all of my address and control signals :
# PadFunction: IO_L8P_T1_33
set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}]
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
set_property PACKAGE_PIN AC12 [get_ports {ddr3_addr[0]}]
It therefore seems logical to me that when I try to generate my IBIS file, it tries to find the SSTL15_F_AUX20_HP model for these signals. But this model does not exist !!!
Two questions :
Is it normal to have the property "VCCAUX_IO HIGH" for cmd/addr signals ?
Can I use SSTL15_F_HP model (which exists) instead ?
Many Thanks
Arnaud

Answer 1

Hi Vinay,
Thanks for the answer ! It seemed logical to me but I wanted to make sure.
In that case, why the SSTL15_F_AUX20_HP model is not defined in the Xilinx IBIS file for the Kintex-7 ?
Electrical standard is SSTL15 (DDR3), my slew is Fast, we are in HP bank and my VccAux_IO = 2.0V.
And if the SSTL15_F_AUX20_HP model is equivalent to the SSTL15_F_HP so the VCCAUX_IO HIGH property has no effect ...
I can not believe I'm the only one to ask ...
Arnaud