NI 9223 at 1Mhz on a cRIO-9024

Hi All,
I'm trying to use the 9223 module to sample at 1Mhz using User-Controlled IO Sampling.
The 9223 should be able to simultaneously sample 4 channels at 1Mhz (that's why I bought it), but I can't get it above 500khz.
I'm using the "NI 9223 User-Controlled IO Sampling" code from the LabView examples (see attached), which works fine with a sampling period of 2 uSec or above, but at 1uSec I get the attached error.
The example code has a warning saying some cRIO controllers can't keep up with 1Mhz rate of the NI 9223. I'm using a cRIO-9024, but I can't find the relevant specs on sampling at 1Mhz for it. Could this be the problem? This cRIO/module combo was recommended to me by a NI rep with one of my requirements being sampling at 1Mhz, so I hope that's not it...
Anything else I can do to get it to run at 1Mhz (or at least at 750khz)?
NI 9223 User-Controlled IO Sampling (Host).vi ‏259 KB
NI 9223 User-Controlled IO Sampling (FPGA).vi ‏128 KB
NI 9233 error msg.png ‏18 KB

Sorry for the late reply. I decided to install LabView 2013 since the code has obvioulsy changed between versions and I hoped it might solve my problems.
In short, the 2013 host code is also different than the 2011 example code. The 2013 code actually works at 1Mhz. However, it does not graph the data continuously. The 2011 code has the graph inside the while loop, while the 2013 code displays it after it acquired all of the samples (outside of the while loop). The number of samples that it can acquire is limited.
In my application I'll be running code on the FPGA at 1Mhz. It will control a voltage output based on input idependent of the host. However, I also need a continuous display of the data on the host and the ability to data log a couple of seconds at a time at the press of a button. This host code is all working, but times out at the 1Mhz that is required to run the FPGA code.
What I am now considering is putting two versions of the FIFO code on the FPGA. One running in a different loop that runs slower that is used to display the data continously and another one that runs at 1Mhz for data logging that will only gets called occasionally and does not need to be continuous.
I'm not completely happy with that solution however, because I'm used to pausing the graph at will to inspect the data and it will mean rewriting of some code.
I've attached the 2013 FPGA example code and 2011 Host example code. Ideally these would work together at 1Mhz (right now it times out at 76 ticks). Any ideas how to get this to work would be greatly appreciated!
Thanks in advance!
2011 Host code.png ‏60 KB
2013 FPGA code.png ‏85 KB

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