VeriStand 2013 Embedded Data Logger with cRIO 9024

I am using VeriStand 2013 with the Embedded Data Logger on a cRIO 9024. I have noticed that when I first deploy after a complete power cycle, the embedded logger works great - responding immediately to a change in the Log Trigger value. However, If I undeploy and then redeploy the project, the embedded data logger appear to casue issues in the communication between the target and the host. The first symptom of this is that the indicators on the workspace appear to begin to lag significantly. The also affect the response of the boolean control that I have for the log trigger which now will not actually turn off when pushed but will rather only respond many seconds or minutes later. When this happens, the log files are also much longer than the intended period.
This problem only gets worse with further undeploy and reploys. However, when I power cycle the cRIO, the net time i open the workspace everything is working great again with no delays.
Any ideas on what could be causing this issue?

Hello Aaron_Smith,
Are you writing to a single file each time? If so then the issue could arise from the file size and the file needing to be loaded into memory each time your redeploy. Try to run the system so that it writes to different files. Also, what is the status of the memory and CPU usage of the device while the application is deployed? Please verify that you are not maxing out the processor or memory as this causes network issues that could result in behavior of this type. Also, would it be possible for you to post a simple example that exhibits the same issue? Please include all files that are necessary to run the system definition.
Wear
National Instruments
Product Support Engineer

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Hi, thanks for your help=) I've manage to drag the file into my targeted controller. I am now doing the setting of the data logger program, but there's one thing I'm unsure of. May I know what does it mean by the cFP controller clock? http://zone.ni.com/devzone/cda/tut/p/id/3219 . Thanks. =)
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Error on RT Get CPU Load With CRIO 9024 and LV2010

I just try to monitor CPU Load on my CRIO 9024 using LV2010 and i get Error -2233 with RT Get CPU Load.vi
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Hi silencer,
Thank you for posting on National Instruments' forum.
Can you tell me your version of LabVIEW RT, and NI-RIO drivers please?
I verified the problem with LabVIEW 2010 and a cRIO 9022 and it works.
Can you send another screenshot please?
Best Regards,
Romain P.
National Instruments France
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>> NIDays 2011, le mardi 8 février au CNIT de Paris La Défense

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Hi, thanks for your help=) I've manage to drag the file into my targeted controller. I am now doing the setting of the data logger program, but there's one thing I'm unsure of. May I know what does it mean by the cFP controller clock? http://zone.ni.com/devzone/cda/tut/p/id/3219 . Thanks. =)
Log On Startup
Start logging when the controller powers up.
Start Log Time
The time to start logging.
Stop Log Time
The time to stop logging.
Note: Make sure the clock is set correctly on the controller. The settings described above refer to the cFP controller clock.
Log Rate
The number of milliseconds to wait between each acquisition.
FP Drive For Data Files
The drive to store the log files in. The C: drive is the default for all cFP controllers. If you want to save to the removable CompactFlash drive on the cFP controller, select the D: drive.
Digital "Pause" Line
The Digital Input item to use as a "pause" button for data logging. Logging pauses when the signal is high. When the signal goes low again, a new file is created and logging continues if appropriate.
Note: Use only Digital Input items for the Digital "Pause" Line.
Tip: You can use DIP Switch 3 to block the current data from being logged. This switch works the same way as the Digital "Pause" line.
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pulsewidth using counter.jpg ‏659 KB

Hello Karthik,
I can think of two ways I would approach this. One would use software timing, and the other would use hardware timing.
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Best Regards,
Doug Norman

Custom device / I am trying to use a vehicle controller model developed in LabVIEW with compactRIO (cRIO-9024)

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Hi,
You should post this on the Veristand Forum.
http://forums.ni.com/t5/NI-VeriStand/bd-p/440
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Using cRIO-9024 serail port can I read the data from AFM60 absolute encoder, multiturn, SSI interface

I would like to request you to kindly address the following quarries.
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Regards
Shantanu
Attachments:
afs60_afm60_english.pdf ‏2298 KB

Hi Shantanu,
To read and write data from the serial port on a cRIO you access the serial port as a VISA resource, there are serial VISA VIs to read and write data on the serial port.
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Regards,
Adam Brown
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melissafromlenexa wrote:
That is not the right device, it is the
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That behavior definitely sounds odd. I would expect models that worlk in previous versions of VeriStand to work with newer ones as well.
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Choosing the Right Network Protocol for CRIO 9024 to PXI over Ethernet

We are in the design phase of setting up a CRIO 9024 Embedded Controller to send data captured to a PXIe-8105 Controller over ethernet. The data will be be 2D arrays of double precision. This data will need to be sent to the pxi at the end of each test step. Each step will have different number of channels and sample rates.
For example, Test Step 1 will have 5 channels of Analog inputs that will be sampled at 100,000 KHz for 1 second. This data will be coming from the CRIO FPGA. The data will get post processed by the CRIO 9024 and analyzed for pass or fail metrics. Then, the CRIO controller will send the 2D Array of Data (500,000 data points 5 X 100,000) and the results of all the metrics (a 1D array) to the PXI.
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I was thinking TCP/IP would work best because of the 2 way communication needed. But then I was looking at Network Streaming or even using Shared Variables.
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Solved!
Go to Solution.

Hi,
You could use either. Whichever you are more comfortable with really. The STM method will have slightly less overhead over my XML style of tagging the data but it will be very little given the data size. Probably go with STM as it just has most of the work done for you.
In terms of data size the way you should normally transfer data like this is to flatten to string. If you convert to a string of human readable numbers you will either lose precision, increase size or both. Given that, the string after being flattened will be the same size as the original array anyway so quick calculation based on your previous post 500,000 doubles (8 bytes) is 4 miB (3.8MB)
Cheers,
James Mc
========
CLA and cRIO Fanatic
wiresmithtech.com/blog

NI 9223 at 1Mhz on a cRIO-9024

Hi All,
I'm trying to use the 9223 module to sample at 1Mhz using User-Controlled IO Sampling.
The 9223 should be able to simultaneously sample 4 channels at 1Mhz (that's why I bought it), but I can't get it above 500khz.
I'm using the "NI 9223 User-Controlled IO Sampling" code from the LabView examples (see attached), which works fine with a sampling period of 2 uSec or above, but at 1uSec I get the attached error.
The example code has a warning saying some cRIO controllers can't keep up with 1Mhz rate of the NI 9223. I'm using a cRIO-9024, but I can't find the relevant specs on sampling at 1Mhz for it. Could this be the problem? This cRIO/module combo was recommended to me by a NI rep with one of my requirements being sampling at 1Mhz, so I hope that's not it...
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Attachments:
NI 9223 User-Controlled IO Sampling (Host).vi ‏259 KB
NI 9223 User-Controlled IO Sampling (FPGA).vi ‏128 KB
NI 9233 error msg.png ‏18 KB

Sorry for the late reply. I decided to install LabView 2013 since the code has obvioulsy changed between versions and I hoped it might solve my problems.
In short, the 2013 host code is also different than the 2011 example code. The 2013 code actually works at 1Mhz. However, it does not graph the data continuously. The 2011 code has the graph inside the while loop, while the 2013 code displays it after it acquired all of the samples (outside of the while loop). The number of samples that it can acquire is limited.
In my application I'll be running code on the FPGA at 1Mhz. It will control a voltage output based on input idependent of the host. However, I also need a continuous display of the data on the host and the ability to data log a couple of seconds at a time at the press of a button. This host code is all working, but times out at the 1Mhz that is required to run the FPGA code.
What I am now considering is putting two versions of the FIFO code on the FPGA. One running in a different loop that runs slower that is used to display the data continously and another one that runs at 1Mhz for data logging that will only gets called occasionally and does not need to be continuous.
I'm not completely happy with that solution however, because I'm used to pausing the graph at will to inspect the data and it will mean rewriting of some code.
I've attached the 2013 FPGA example code and 2011 Host example code. Ideally these would work together at 1Mhz (right now it times out at 76 ticks). Any ideas how to get this to work would be greatly appreciated!
Thanks in advance!
Attachments:
2011 Host code.png ‏60 KB
2013 FPGA code.png ‏85 KB

VeriStand 2013 Embedded Data Logger with cRIO 9024

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