Ni pci-6602 PFI pins and io register configurat​ion

Hello, I am a new user of pci-6602 board and I am using matlab xPC.  I would like to use some PFI pins as digital output. I am not sure about what to do after configuration I/O Register. I configured I/O Register for inputs and outputs. Then which register should i use for sending data? SW Save register or else? And  do i have to do anything with  I/O Window registers? This not clear  in manual. I need  help in this issue.
Thanks

 Hi bckr,
 There is additional examples and documentation available with the NI Measurement Hardware Driver Development Kit. This includes example code and links to the documentation.
 I would advise posting any questions you have after that to the Driver Development Kit forums. This is where you will find people actively supporting register level programming with the 660x boards.
 It looks like you use GO_Load_A_Registers.writeGO_Load_A command to load the register after initializing the MITE board.
 If you have any further questions then please post them to the Driver Development Kit forum, that is where you will receive the best support.
 Have a great evening,
 MatthewW
 Applications Engineer
 National Instruments

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    I've tried a range of things, from starting the two-edge measurement task before the firing signal is sent, to trying to force things with a timed sequence, to doing things with brute force via a seuqence structure. When I try to start the two-edge measurement task first, though, the firing signal isn't sent until the counters time out. This of course, wrecks the experiment, because all of the timing is then messed up. The VI that I've attached (Version 1.vi) is a HIGHLY simplified version of the initial attempt I made at doing this, with all sorts of background stuff removed just so I can cut to the chase. (Only one two-edge measurement task is shown, for instance.)  I think that the VI is pretty self-explanatory (and embarrassingly primitive), so it probably doesn't need much in the way of explanation. Counter 7 and PFI 0 on the 6602 are used to accept the signal from the firing button and trigger the event structure, which contains the two-edge separation and gun-firing tasks. (In reality, I use a separate VI to have three to four concurrent two-edge separation tasks running concurrently, one for each velocity station.) I start the two-edge separation tasks first so the detectors and counters are ready for the projectile. It's not necessary here, but I kept the 500 ms wait frame in this example because that's why the sequence structure exists -- to allow the shutter of the Nikon to open completely before the gun fires. After those 500 ms, the firing signal is sent to the circuit that actually fires the gun.
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    FINALLY, my question: What am I doing wrong, here? If I put the two-edge separation tasks in the same frame of the sequence structure as the firing task, the gun fires when it's supposed to, but we get no velocity measurements. I've also tried to force the timing with another version of a sequence structure; I'm attaching another very simplified version below as Fire and speed example.vi.
    After you recover from your violent fits of laughter, I'd really appreciate hearing what you might recommend. (And no, surrender isn't an option.)
    Thanks for taking all of your valuable time to read this huge post -- I really appreciate it!
    Mark
    Attachments:
    4044, cropped.jpg ‏197 KB
    Version 1.vi ‏35 KB
    Fire and speed example.vi ‏30 KB

    I agree with all 3 of Kevin's points.  His first suggestion will probably fix your problem (see below).  The 2nd and 3rd suggestion would improve efficiency and responsiveness, but #2 might not be possible since independently triggering four outputs in hardware would require the use of 4 counters (on the 6602 anyway) which might be busy doing other tasks in your application (although if you don't need the stations to trigger independently then you could implement this with a single counter).
    I think I have an explanation of the problematic behavior you are seeing based off of the following bits of information from your post:
    1.  Running the small example code by itself works flawlessly, but adding other simultaneous functionality fails.  You mentioned you are doing this on 4 stations, so I'm assuming 4 counter input tasks running in parallel.
    2.  The behavior you are seeing is that the 2nd sequence does not execute until after the read times out (note that the sequence is supposed to be executing in parallel with the read).
    It sounds like the problem is coming from a combination of calling into DAQmx Read before data is available (this consumes one of the threads that LabVIEW has allocated to your application until DAQmx Read finishes executing) along with the fact that LabVIEW allocates 4 threads per execution system per priority by default.  Since all of your threads (from what I can tell) are executing on the same priority, the 4 reads you are calling will block anything else from executing until they have completed.  By then it's too late and the firing of your gun happens after the counter task has already timed out.
    You *may* increase the number of threads allocated to your application by using a VI that is included with LabVIEW (vi.lib\Utility\sysinfo.llb\threadconfig.vi) and this would also probably remedy the behavior you are seeing.  However, rather than throwing more threads at this application I think the better solution would be to change the sequencing of your tasks like Kevin suggested ("create and start the 2-edge task before entering the sequence structure, and defer the 2-edge *reading* until *after* firing the DO")--in doing this you would now expect to see data immediately upon calling DAQmx Read and you avoid the situation where Read is blocking indefinitely and consuming an application thread.  You could take this a step further by checking the Available Samples per Channel property (or using the DAQmx EveryNSamplesAcquiredIntoBuffer event) to ensure that data is actually available before calling Read.
    Best Regards,
    John Passiak

  • How to generate a pulse on x number of events PCI-6602

    I am running LabVIEW 5.1 full development with a PCI-6602 counter board.
    I would like to generate an output pulse after counting x number of input pulses. I would also like to reset the counter with an external signal.
    My application is I am trying to generate a second index pulse for an encoder.
    I would like to count the pulses from encoder phase A and generate an output pulse on x number of counts. Then I would like to reset the counter using the encoder’s index pulse. This way I can change the phase of the “generated” index pulse with respect to the “real” index pulse by x number of counts (degrees) and maintain that regardless of encoder rpm.
    Thanks
    Brian

    Brian,
    There actually is a way to do what  you want, but it gets a little complicated.  I don't have LV on this machine so I'll have to just describe the idea.  First a summary: the counter will repeatedly countdown to 0.  Each time it reaches 0, it will generate a brief pulse which will in turn hw-reset the counter value to N.  Then it will countdown to 0 again, etc.  The same brief pulse could also be wired to a different encoder-measuring counter to create a "delayed" reset to 0 (or some other #).
    1. Configure your counter for "position measurement" instead of "simple event counting".  Set the encoder type to, um, I forget the name -- something like "two pulse encoder."  It's the setting that will increment with every SOURCE edge and decrement with every AUX edge.  Wire your encoder channel A to the counter's default AUX input (in position encoder mode, you must use the default input pins).  Hard wire from the default SOURCE input to GND.  Now every encoder edge will decrement the count, and nothing wlil ever increment it.
    2. Configure the counter to use z-indexing.  Set the z-index reload value to be N-1, where N is the # of encoder counts by which to delay the encoder's real z-index pulse.  Set the z-index reload phase appropriately, probably to A low B low.  Wire the real z-index pulse to the counter's GATE input.
    3.  Configure the counter to "pulse on terminal count" -- you do this using 'Counter Set Attribute.vi'.  So N encoder edges after the real z-index pulse, you'll generate a pseudo-z-index with this counter.
    4. You can wire this pseudo-z-index to the GATE input of the encoder-measuring counter.  Now the encoder's z-index pulse is delayed by an amount you can program.
    5. Note: this method requires the motion to be uni-directional.
    Good luck!
    -Kevin P.

  • Count digital events on a Counter with pci-6602 with callback on CVI

    Hi,
    I'm using a PCI-6602 card with CVI 8.5 and I need to trig on event.
    On every pulse I received, I need to do some actions like increasing a counter, send a message on Rs232 etc.. I don't want to do any loop checking that the counter value has changed. I would like to use a callback to execute this code only on the edge or counter value event.
    My problem is that I don't know which function can do this. Is there any way to get an event on a pci-6602? 
     Thanks 
    James 
    Solved!
    Go to Solution.

    Hello.
    It's completely possible to create a callback that will allow you to do what you want when a edge will occur on an external signal you define.
    To do this, you can for exemple create a counting edges task that will use one of the 6602 counters,and the set your external signal to be the source of your sample clock.You'll then be able to register a callback with the function DAQmxRegisterSignalEvent, and your callback will be called each time an edge will occur on your specified sample clock source.
    Here's 2 links that explain the events in DAQmx and how to handle them in CVI. The example ReadDigChan-ChangeDetectionEvent.pr that ships with DAQmx examples (Hardware Input and Output<<DAQmx<<Digital measurements) can be very useful to understand how to do. This example creates a signal event callback to detect change detection for digital inputs.
    Regards.

  • 6602 Save Registers and FIFO

    Hello,
    I've been searching through the forums and noticed that their are many oppinions concerning the size of the onboard memory buffer for the PCI-6602 board.  Some say the board has a 1 or 2 sample buffer (FIFO) while others say the board has a 16 sample FIFO.  I was hoping someone could clear this up for me.
    Lets assume that we are running a buffered event counting measurement using DMA transfers.  What I understand from the register level programming manual is that the counter has two save registers (Gi HW, and Gi SW).  When a gate signal latches the counters count, it places it into one of these registers.  The next count would be placed into the second save register.  My understanding is that the DMA transfer, sends the data in the save registers directly to the internal buffer configured by the user on the computer running the DAQ software.  This would mean that the save registers on the card are the FIFO buffer that everyone talks about, and thus the card only has a 2 sample buffers because each counter only has 2 save registers which each hold only one 32bit number.  Is this correct?
    If it is not, then what happens?  If it is correct, then where did this idea of a 16 sample FIFO buffer come from?
    Thank you for your help,
    Matt
    Attachments:
    NI 660x Register level Programmer Manual.pdf ‏868 KB

    Hello Matt,
    You are correct each counter has 2 sample FIFO and here
    is the data flow.
    Counter register -> 2 Sample FIFO on 6602 ->
    Transferred across PCI Bus using DMA -> RAM Buffer -> Read by software
    I did see the forum post which says about 16 FIFO for a
    TIO board, but could not find any documentation on that. Apart from that here is the knowledgebasethat talks about the buffer size of 660x boards. 
    Thanks
    nAyer

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