Pci 6132 digital signal using counter

Hello,
I want to give digital short pulse (around 10 us) in frequency of 10 Hz.
i tried to creat digital waveform and to use the wait(ms) sub vi in labview but it's very inaccurate..
sombody told me to use counter but i don't know exactly how.. i saw some expamle of accuaring sigital signal using counter but o coudnt understand it completly.
any help by ver appricieate.
thanks,
Etay

Hello, etay23!
Were you able to check out the example? Do you have any questions for us about it?
Will Hilzinger | Switch Product Support Engineer | National Instruments

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Generate complementary digital signals with dead time between each pulse and controlled by duty ratio

I am to generate two complementary digital signals using NI 9606 conected by RIO Mezannine Card to NI 9683 (Half Bridge DO).
I am able to generate the signals but I am not able to put dead time between high and low signal and also, low and high signal.
Requirement:
(1) When the first signal goes high and the second signal goes low, there should be a controllable dead time.
(2) Also when the second signal goes high and the first signal goes low, there should be a controllable dead time.
I am able to do requirement 1, but I am unable to fulfill requirement 2.
Please have a look at my VI and let me know how to go about satisfying requirement 2.
Attachments:
complementary test 2.vi ‏69 KB

Hi Frank ,
I have already taken note of the example Tannerite has provided and have built my vi ( attached in previous post) surrounding that example.
Now I require to control the PWM duty cycle as you can see from the vi using a knob and that control refers to both the signal 1 and 2.
Now the signal 1 end and signal 2 generation requires a controllable dead time. Similarly, signal 2 end and signal 1 geneeration also requires another controllable dead time.
I am able to do either one dead time at a time using delay but not two dead time simultaneously.
I feel that I have two put the delays at the appropriate data flow point. I am working on that.
I would really appreciate if you could give some insight on how to solve this dead time issue and generate two complementary waveform with dead times whose duty cycle can be controlled by a knob controller in fronty panel .
I have also posted the required timing diagram for reference as suggested by Tannerite.
Best regards.

Pci 6132: counter too sensitive?

I'm using the pci 6132 to sample a microphone, with analog triggering on that same input channel.
At the same time, parallel, I need to follow an index of a conveyor belt on which the samples move, so I can track which mic signal corresponds to which sample.
It seems that because I'm using a trigger on the analog inputs, I couldn't use CTR0, so I'm using CTR1 (on PFI3) to track the conveyor steps.
The problem is that this counter is _very_ sensitive. I count 4-9 edges where there should have been one. so I had to implement code to check the timing of the steps and to manually increment a variable, instead of using the counter output directly.
The device doesn't support 'digital filter', I already tried adding capacitors to the hardware to clean up the signal of noise, see attached image. Not much or no improvements though.
I have the same results in MAX-testpanel.
Is there a way to configure a hysteresis, or any other option to control the counter better? Am I making another mistake? Or is this card just not suited for the job?
Attachments:
pci6132_counter_input.PNG ‏37 KB

The slow edge was a result of me adding a capacitor, in an attempt to clean up the signal.
I removed them, and now I get a little better results, only once every 10 (falling or rising, seems to make little difference) I see the counter count multiple edges for only one step of the conveyor.
In the attached image, the signal without capacitor, you can see now in the rising edge a little downward spike, right before the edge starts. This was the reason I tried the capacitor. But given I have the same problem for rising or falling edge, my problem might be something else.
In the basic LV-example, there is a 'wait until multiple' in the while-loop, and this seems to work, or at least give a lot less miscounts... I'm confused by this, I thought the counting happened on the device and the while loop only 'asks the counters value every iteration'.
So how can a 'wait' in this loop help avoiding the multiple counts?
Btw: my connection is as follows: 24Vdc signal comes from the conveyor, into an optocoupler. The optocoupler is connected to PFI3, with +5V and a pulldown resistor to DGND (see second image)
Attachments:
pci6132_counter_input_no_capacitor.PNG ‏38 KB
Counter_connection.PNG ‏4 KB

How to check 6 digital signals change value at the same time with PCI-6229??

I am using DAQ card PCI-6229.
Channel 1 generate a digital signal.
Channel 2,3,4,5,6,7 acquire digital signals.
I want to check:
1. Whether the rising edge of Channel 2,3,4,5,6,7 occures at the same time;
2. The time delay from the rising edge of Channel 1 to the rising edge of Channel 2,3,4,5,6,7 is within a certain range.
I know I can use counter to get the two edge seperation time delay. But I only have two counter, it is two time-consuming if I check one by one.
I don't know how to check the rising edge of 6 different channels occure at the same time.
Does anyone has any suggestions?
Thanks

Hello,
You can use the DAQ card's digital input change detection circuitry to detect changes in the input, you can then use a counter to measure the relative time between samples. Please read Page 6-9 DI Change Detection Applications for more information. Let me know if this helps
Christian A
National Instruments
Applications Engineer

Digital Signal Modification (PCIe 6320)

Hi,
We've got a digital signal which is basically a series of trigger pulses for a receiving device, constantly pulsing. However, the pulses need to be modified so that e.g. only every third pulse ends up on the receiving device, but not more than e.g. 4 pulses, with a given delay of e.g. 2 pulses.
Using this example, input and output signal should look the following:
in : 1---1---1---1---1---1---1---1---1---1---1---1---1---1---1---1
out: --------1-----------1-----------1-----------1----------------
We've got it basically working using Digital Edge Counting and connecting/disconnecting terminals as needed. However, the task is very time critical and I'm seeking for a solution that works as close to hardware as possible (ideally, the task should be carried out by the card itself after setting up the parameters).
We've got a PCIe 6320 that we want to use for this task, we are programming in C using the DAQmx C library.
Thanks for your suggestions.

Since your real code is different than what was posted, I can only take some guesses for why you can't count more than (about?) 1 million pulses.
1. If your real code doesn't wire a "# of samples" value to DAQmx Timing.vi, then a continuous task that is told it's acquiring at 100 MHz will use a default buffer size of 1 million samples. You can create a bigger buffer by wiring in a bigger value. You can also loop over your Read calls to help prevent a buffer overflow.
2. Theres a limit to the rate you can stream data from the board to system RAM. The X-series is very VERY much better than most of its predecessors in this regard for counter-based measurements. (See this thread and associated links.) But it still won't handle 100 MHz effective sampling rates for any appreciable duration.
3. Another option I've seen used is count binning. That method works kinda inside-out from your method by letting the external pulses increment the count while that count is sampled at a constant sample rate.
4. I haven't yet been able to do any real-life playing with an X-series board, but I think there's also a mode for measuring precise frequency while sampling at a constant rate. That mode might prove useful for you as well.
-Kevin P

Can source and gate used to measure 2 signals using one counter?

I have one PCI 6602 card to measure measure the frequency. PCI 6602 has 10 channels, in which channel 5 and 10 doesn't have 'source' terminal.
We have to measure frequency from 16 signals using one PCI 6602.
From channel 1 to 4 and 6 to 9, we have 8 'Gate' and 8 'Source' terminals.
We have connected 16 signals to these 16 terminals.
At any given point of the time we want to measure either 'Gate' signals(8) or 'Source' signals(8).
Can any provide any guidance to make a program in labview to measure frequency (period) as per above given points?
Regards
Vijay

Hello Vijay,
It takes one counter for each digital frequency you want to measure and the PCI-6602 has 8 counters total. This means that the maximum number of digital frequencies you can measure is 8. If you want to measure 16 frequencies you'll need 16 counters.
Single counter frequency measurements are made by comparing the board's time base (80 MHz) to an external frequency. The board counts the number of time base periods that occur during one period of your incoming frequency. When you configure the board to take a single counter frequency measurement the card routes the time base to the source of the counter and then you connect the frequency you want to measure to the gate of the counter.
Here are a couple of articles that explain how these measurements are taken and calculated. (The second article is on period measurements so for frequency measurements you measure period and take the inverse):
Making Accurate Frequency Measurements
Period Measurements with a Counter
There are example programs available in the LabVIEW example finder. You can locate these by going to Help>> Find Examples... The examples you want is: Hardware Input and Output>> DAQmx>> Counter Measurements>> Digital Frequency>> Measure Digital Frequency- Low Freq 1 Ctr.vi.
I hope this explains how counters work and why you need one counter per measurement.
Cheers,
Brooks

How to use counter using PCI 6259

Hello, users,
I have a PCI 6259 board and use Labview 7.1.
I'd like to repetitively count the photon signals at 10ms integration time. I want cumulative counts in every 1 sec (1000ms) (or 1 min (60000ms)) And I want to save counts into txt.file which is open in excel program.
I am a beginner to use counter using PCI 6259 board.
1. Could you explain default NI-DAQmx counter terminals, i.e., CTR 0 SRC, CTR 0 GATE, CTR 0 AUX, and CTR 0 OUT?
2. How do I use them or how can I connect to count TTL pulse using PCI 6259?
3. As I mention my purpose above, which example is the first step to start working my purpose?
4. If you know good example, could you tell me about that?
5. If anyone has labview example which is similar to my aim, could you give me some tips or your examples?
Any hint, comment or advice would be appreciated.
Thank you so much for your response.
Leek2

I have never used the PCI 6259 but have used counters many times with labview, the coding should be the same independent of the board. What you want to do is finite buffered edge counting using a internal clock. The best way to do this is to look at the examples programs and use the express vi to get started, then you can use this code to customize your program exactly as you need.
To address your questions:
1. CTR0 means "counter 0" the name of the physical resource sometimes listed at GPCTR0. Each counter has 4 connections to the outside world:
source "src"(for counting input TTL signals),
gate (for synchronizing to external clocks and edges),
out (for pulse-train out operations)
and aux (specialty operations such as up/down counting and encoding)
2.For event counting with internal clocking you will only use the src this is the input from the signal you wish to count (ie PMT discriminator for photon counting).
3,4,5. Look at the count edge examples, there isn't one that does exactly what you want but I have done this with a 6602 (it has e counters) where I use one set of counters to set up a finite pulse train in your case 1000Hz with 1000 pulses, and another counter to edge count on an external pulse, with the source of this pulse routed from the out of the other counter. Then you can start the task and read when 1000 samples are in the buffer (about 1 second later).
Hope this helps,
Paul
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA

Counter Output as Sample Clock of Digital Signals

I have a situation where I need to use a hardware counter as sample clock of digital output signals.
How do you specify the "Counter Internal Output" signal as a sample clock of digital output?
I want to do something like this:
// Create counter task
  CNiDAQmxTask m_Task(_T("ATask"));
  m_Task.COChannels.CreatePulseChannelTicks(_T("Dev1/ctr0"), "", _T("20MHzTimebase"), DAQmxCOPulseIdleStateLow, 0, 10, 10);
  m_Task.Triggers.StartTrigger.ConfigureDigitalEdgeTrigger("PFI0", DAQmxDigitalEdgeStartTriggerEdgeRising);
// Create digital output task
  CNiDAQmxTask m_Task2(_T("ATask2"));
  m_Task2.DOChannels.CreateChannel("Dev1/port0/line0", "", DAQmxOneChannelForAllLines);
  m_Task2.Timing.ConfigureSampleClock("XXXXXX", 0, DAQmxSampleClockActiveEdgeRising, DAQmxSampleQuantityModeFiniteSamples, 400);
How do I specificy "counter 0 Internal Output signal" instead of "XXXXXX" above, i.e. the sample clock of the digital output signal. Can't find the name of the signal anywhere in the documentation and help files. I have a 6259 DAQ board.
/pek

Thank you for your answers, but I can't get it to work.
When I use "ai/SampleClock" as sample clock everything works correct. When I try to use a counter as sample clock the task completes imediately, before any digital signals has been sent/measured. The task even completes before I have started the trigger, which is very confusing. No error appears.
I think that something is wrong about how I setup the counter. I use the code below:
// Create counter task
CNiDAQmxTask m_Task(_T("ATask"));
m_Task.COChannels.CreatePulseChannelTicks(_T("Dev1/ctr0"), "", _T("20MHzTimebase"), DAQmxCOPulseIdleStateLow, 0, 100, 100);
m_Task.Triggers.StartTrigger.ConfigureDigitalEdgeTrigger("PFI0", DAQmxDigitalEdgeStartTriggerEdgeRising);
// Create digital output task
// The code below works with "ai/SampleClock" as sample clock
CNiDAQmxTask m_Task3(_T("ATask3"));
m_Task3.DOChannels.CreateChannel("Dev1/port0/line0", "", DAQmxOneChannelForAllLines);
m_Task3.Timing.ConfigureSampleClock("Dev1/Ctr0InternalOutput" /*"ai/SampleClock"*/, 0, DAQmxSampleClockActiveEdgeRising, DAQmxSampleQuantityModeFiniteSamples, 400);
// Create samples
CNiUInt32Vector ui_data;
for(int i = 0; i < 200; i++)
for(unsigned int j = 0; j < 2; j++)
    ui_data.Append(j);
// Create digital writer
CNiDAQmxDigitalSingleChannelWriter m_writer3(m_Task3.Stream);
m_writer3.WriteMultiSamplePortAsync(true, ui_data);
// Wait until task completes
m_Task3.WaitUntilDone(-1);

Measure rpm and PWM signals using digital input of NI9401 module

Hi, is there a simple way how measure rpm (to 5000 rpm) and PWM (about f=3kHz) signals using digital input of NI9401 (ultrahigh-speed digital I/O) module plugged in NI 9172 ? I will wellcome any suggestions and VI examples (bether still). I'm begginer using LView 8.2. I apologize for my poor English. Many thanks.

Hi CUA,
Since you have already the right tools, you just need to get started with the software. The NI-9401 will give you access to the counters that are inside the cDAQ chassis 9172.
You need to place the module in slots 5 or 6. You can read in how they work and how to configure them in the counters section of the user guide found here.
Now to measure rpm, you can either measure the period of the signal (seconds) and multiply by 60 to have minutes and the number of ticks per revolution. You can find a shipped example to read period called “Meas Dig Freq-Buffered-Cont-Large Range 2 Ctr.vi” found under Hardware Input and Output » DAQmx » Counter Mesurements
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There is great information for these kind of task at this page or just post back if you need to.
Hope this helps.
Gerardo O.
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National Instruments

How can I implement a Digital I/O counter with a maximum source frequency of 80 MHz (like 6602 board) using CompactRIO?

How can I implement a Digital I/O counter with a maximum source frequency of 80 MHz (like 6602 board) using CompactRIO? It appears as if the Digital I/O modules for CompactRIO are much slower than this.
Thank you,
--Ray

Hi Ray,
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Chris E.
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National Instruments
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How to control a digital output signal using the DAQ assistant?

I am using a USB 6251 DAQ board and would like to control a switch. I am gathering airflow, pressure, and acoustic data on the same board (analog input) and would like the switch to trigger when the airflow value is within a pre-determined range. Finally, I would like to reverse the polarity of the switch (to off) about a second after the initial digital signal, all of which is during continuous data acquisition.
I am able to actuate the switch only when pressing the "run" button in the DAQ assistant window. I am proficient with data acquisition but have never tried programming an output... Please help!
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-a troubled researcher
P.S. I am running LabVIEW 8.5 as well.

blsmith4,
You probably won't get the control of the digital port on your card by only using the DAQ Assistant. One of the following examples should provide you the functionality that you would like out of the box:
Digital - SW - Timed Output (Simple)
Digital - Continuous Output (More Complex)
Continuous Write Digital Port - External Clock - Non Regeneration (Most Complex)
Let me know if these work better for you.
Best,
Jason M.
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National Instruments

Is there any tutorial for using ARM cortex-A processors of Zynq for digital signal processing ?

Hello, everyone.
Is there any tutorial for using ARM cortex-A processors(such as A9 and A53) of Zynq to deal with digital signal processing problems?
Please tell me , thanks.

Hi
Check below links
http://www.xilinx.com/training/zynq/software-acceleration-for-dsp-functions-with-zynq.htm
https://www.youtube.com/watch?v=ErEG7ZREcJQ
http://www.xilinx.com/support/documentation/application_notes/xapp1170-zynq-hls.pdf
http://www.xilinx.com/support/documentation/application_notes/xapp890-zynq-sobel-vivado-hls.pdf
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Can i convert a wav file to a digital signal without using DAQ?

i tried the coversion of a sine wave to digital signal, ofcourse it doesnt work on converting wav file to a digital signal. i am also new in labview. i tried to explore it but there are many functions that i can't use.
so my these are my questions.
1) is a .wav file is an analog signal?
2) can i convert it without using any DAQ device?
tnx guys! i'll post the programs that uses quantization of a simple sine wave. i tried it to .wav file but it didnt work.
Attachments:
act04-02.vi ‏41 KB

.WAV is a digital "signal". It uses Pulse Code Modulation to encode analog signal. You don't need a DAQ device to "convert" it to analog. Any computer with a sound card, and media player can "convert" a .wav file to the analog audio signal it represents
Wan L
Applications Engineer
National Instruments
http://www.ni.com/support

Sending analog signals using SCXI bus to SCXI-1600 for digitizing

I want to measure a signal generated in the SCXI-1181 custom bread board module.
Is it possible to send the signal using SCXI bus to SCXI-1600.
The signal is less than +5V & is positive.
Is it possible to use AB0+ & ABO- in SCXI bus for this purpose?
I have a SCXI-1001 chassis installed with SCXI-1600 in slot 1 & SCXI-1181 in slot 2.
I have 4 more switch modules (SCXI-1160s) installed from slot 3 to 6.
Will the above has an interference when you want to control the switches?

see here:
http://forums.ni.com/ni/board/message?board.id=250&message.id=20644

FPGA Digital Signal Output Problem

Hi,
I am having a problem outputting a signal through my PCI-7831 and would appreciate any advice anyone has as I am beginning to crack the wall where I am banging my head into it.
My software is LV7.1 with FPGA module 1.1. I am controlling a VI compiled onto the PCI-7831 with a host VI in windows. I am viewing the outputs I mention on a high end oscilloscope. I'm relatively new to LV and very new to the FPGA module.
The FPGA VI consists of 3 while loops though only 2 loops are not performing as expected. The FPGA while loops in question contain a single sequence structure that has as their first frames an IRQ 0 and 1 respectively .
In the host VI I am waiting for IRQ, writing the value of 2 wait timers, and acknowledging the IRQ in the first frame of a sequence. The FPGA then sets the states of 2 DIO outputs to both high. Then the timers keep both outputs high until the next frame is reached, then 1,0 is written, the second wait expires, and the loop repeats until the while loop conditions in the host VI are met and the sequence in the host VI indexes (this is about 1 second.)
For the second loop, I am going to the next frame in the host VI. This host works the same as the above sequence but only 1 value is being written, 0,1.
In any case, it works but has 2 bugs I can't reason.
The last, and only the last, iteration of the "both high" period is wrong. The 1,1 becomes 1,1, then 0,1 about halfway through the wait, then the 1,0 occurs properly, then the 0,1 period begins properly.
The other bug is that at the beginning of the 1,1; 1,0 sequence the 1,0 is repeated twice.
I am using these signals to control a custom high amplitude bipolar digital signal generator.
I have posted my VI's if anyone would like to see them.
Thanks,
Ben
Message Edited by bugsmashers on 07-21-2005 12:57 PM
Message Edited by bugsmashers on 07-21-2005 12:58 PM
Attachments:
Preset_power_top_WHILE_loops1.vi ‏311 KB
Digital Pulse Amplitude Control Preset Power.vi ‏216 KB
preset_power_data_gen_FPGA.vi ‏684 KB

Hi Ben-
I took a look at your code, and I can explain the first error you are talking about, but I don't think I understand the second error. For the first error, lets start on the last iteration of the first while loop in your host code. It first waits on IRQ 0, then sets the 'high' and 'low' parameters on RT, then acknowledges IRQ 0. At this point on the FPGA side, the top loop (1,1 loop) begins to execute and sets the lines to 1,1. Meanwhile back on the host, your first loop completes and the second loop starts. The first thing the second loop does is wait on IRQ 1. It doesn't have to wait at all because IRQ 1 was set long ago when the FPGA program started, so it clears IRQ 1, and the second FPGA Loop immediately sets the lines to 0,1. The next thing that happens is your top loop in FPGA (1,1 loop) finishes waiting for the time specified in 'high' and moves to the next sequence frame and sets the lines to 1,0, next the second loop finishes its wait ('Wait Zero') starts the loop over again, sends IRQ 1, which is handled by your second host loop, it acknowledges IRQ 1, and then your second FPGA loop sets the lines back to 0,1. Long explanation, but I hope not too confusing. Synchronizing the host and FPGA with everything happening in parallel can get to be a lot to wrap your brain around.
One comment on the code - From your description and looking at the code it looks like the first pulse iterates for a given period of time, then the second. The way you have it written right now the pulse period will not be very deterministic - especially if you are using windows as your host. The reason is that every iteration of the pulse depends on an IRQ interaction, which means you are waiting on your host CPU to do something. Granted, the host should react quickly, but it is not deterministic - if windows is your host, and you start dragging windows around, you'll notice your period become longer than 'high'+'low'. A better architecture might be to send the number of iterates of the 1,1 - 1,0 loop you want to execute down to FPGA, and let FPGA count the iterations and report back when it's done. Then start the second loop, or send all the info down to FPGA and let it control both loops. If setting 'high', 'low', and 'wait zero' need to happen through out, use the read/write control to just update those on the fly from the host rather than making the FPGA halt while they are updated. If determinism on the period length is not important for your code, or you designed it the way you did for other reasons, then ignore everything I just said .
Good luck, sorry I couldn't help on the second problem, if it's still an issue, post back with a little more detail on what '1,0 is repeated twice' means
Dustin

Pci 6132 digital signal using counter

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