PCIe comes up but link width is reduced

using Vivado to implment on a Kintex-7 device a PCIe hard core. Got to load and have our linux machine recognize the device. It can see that it is a 4x width device but the LnkSta is 1x. user_link_up is high and when going through debug guide (AR 56616), it only give direction if user_link_up is high and core not seen. I can see the core and my user_link_up is high so any ideas of things to try to debug this.
Should note this is a new board design not on a Dev. board .

I seem to recall debugging a similar issue and finding that you can get a little more information on why the additional lanes did not link up. In my case it happened quite early in the process and I found that the boards were mis-manufactured with some lanes coupled with 10 nF caps instead of the required 100 nF caps. These need to be sized correctly for the PCIe lane detection scheme where the transmitters sense the load to determine which lanes are physically connected.

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Problem of PCI express link width and speed

hello,
I instantiate the pci express core v1.7 into a pci express endpoint and the core was configured as GEN I x8 or GEN II x4. By using the example design Xilinx offered in the ipcore dir, I could read and write device by PIO mode.
However, when I check the device’s link width and speed by using lspci –vvvv in Linux, I found that no matter what configurations I set, the device link is always trained as GEN I x1, which means the throughput of device, reduce 8 times. May the most important problem is that all logic in the user layer upon transaction layer are written at 250MHz, and if link width and speed are limited 2.5G/T and x1, I need to change user logic circuit which is a huge work.
So my question is how to change the PCI express link width and speed in OS side, or I need to change a new motherboard?
(I guess it related with motherboard, and I check that the PCI express slot in motherboard support GEN II X16. Another issue, when I insert a PCI express GEN II x8 device, the device is also trained as GEN I x1).
lscpi -vvvv
01:00.0 RAM memory: Xilinx Corporation Device 6018
Subsystem: Xilinx Corporation Device 0007
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 16
Region 0: Memory at dfcff800 (32-bit, non-prefetchable) [size=2K]
Region 1: Memory at de000000 (32-bit, non-prefetchable) [size=16M]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [60] Express (v2) Endpoint, MSI 01
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal+ Fatal+ Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited
ClockPM- Surprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range B, TimeoutDis-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v1] Device Serial Number 00-00-00-01-01-00-0a-35
Kernel driver in use: card

I also have this issue of the user_link_up is high and everything looks good but the LnkSta widht is 1x. did you ever get any guidance about this?

Why my PCIE Link Width is only x1 instead of x16

Hi Everyone,
I've got a MSI6600GT 128mb installed in my MSI K8N SLI (7185). During bootup i noticed that my bios reporting that the 6600GT is having a link width of only x1. However when go into windows it reported that i have a x16 link width under the windows advanced tab.
I have the following : MSI K8N (7185)
AMD 3200+ (venice) o/c 2180
APACER DDR400 1Gig RAM
WD SATA 160GB
MSI6600GT 128mb DDR3 o/c Core: 560 Mhz
Ram: 1160 Mhz
Forceware : 77.77, 82.15
My 3D Mark score really sux compared to others that have similiar if not lower that than mine. Plus i even O/C my cpu, ram and graphics cards and yet i still get a low score compared to others. ANd yes my system is stable cause i use Prime95 (blend mode) for 3 hours and i play FEAR and Oblivion without crashing (medium setting of course :P).
3dmark 05 (3d test only) at 1024x768 = 2515
Could the link width be the problem??? Can some1 please help me if i can chabge the PCIE link with to x16.

Hi Richard,
Thanks for the reply. But according to an article on AMD websites, it tells a different story. Here an excerpt of it :
"The PCIE specification defines x1, x2, x4, x8, x12, x16, and x32 link widths. The x1 PCIE link was designed to replace the PCI bus. The x16 link is intended to replace AGP*. The x32 link remains unimplemented.
PCIE's potential bandwidth will change the design of the typical PC and encourage the creation of more bandwidth-intensive applications.
* AGP, which was designed to take some of the load off PCI, is similar to PCI and shares some of the same problems – however, it does have some distinctive features. AGP was created specifically for graphics cards and designed to share a portion of main memory to store rendering data, rather than having to load the data into the onboard video memory. New generation video cards sometimes require two separate power connectors, because they outstrip AGP's energy supply capabilities. While the AGP bus can supply a maximum of 25 watts, PCIE can supply 60 watts now and up to 75 watts in the future, thus cutting the need for extra cables. "
Article: http://www.amd.com/us-en/Processors/ComputingSolutions/0,,30_288_13265_13295%5E13334,00.html
Therefore, my PCIE Link should be x16 since x16 is designed for graphic cards??? Isnt x1 tells us the bandwith throughput isntead of how many cards it can support???
Can someone explain to me in more detailed manner regarding thsi issue and wether my MB got it wrong in assigning my VGA card to x1 instead of x16?. Also on MSI website it listed the 6600GT as a PCIEx16 device.
Please help as any help is very much appreciated.
Bset Regards,
The newbie guy

Neo4-Fi PCI-e VGA Link width x8 problem

motherboard: K8N Neo4-FI
processor: AMD Athlon64 3200+
ram: 2 x 1GB
power supply: Antec True Power Quattro 850
vga: Sapphire HD2600 XT 256MB PCI-e
sound: Creative Audigy 2 Platinum
raid: Highpoint RocketRAID 133
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case: Chieftec BA-02B-B-B
fdd: ?
fans: 2 x 12cm, 5 x 8cm
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DVD+-RW: Pioneer DVR109
Here is my problem. I had Vga Sapphire x1300. Link width was x16 and everything worked fine. Now I have bought new vga card Sapphire HD2600 XT 256MB and now the PCI-e vga link width is x8. The motherboard is not SLI and there is only one PCI-e x16 slot. The graphic card works and the card itself is x16. PCI-e is x16. So PCI-e vga link width should say x16 as it has with my old card, but it says x8. I have updated BIOS to the latest version. I have searched the manual but I didn't find anything about setting up the graphic card bus. BIOS has setting for PCIE Spread Spectrum which can be set to "Down Spread" or "Disabled". The second setting for PCIE is PCIE Clock which can be in range from 100-145MHz. I didn't changed these settings because with an old card everything worked fine, and I don't know what these settings mean. Are one of this two settings related to my problem? I haven't overclock any of my components.
Can someone please help me or suggest what to do?
Thanks in advance!
Daniel

Quote from: daniel66 on 19-March-08, 03:05:03
I did what you said and it worked. I pulled the card out and inserted it again. Pushed it a little bit harder in the slot and now it says x16 like it use to.
Thanks again!
Daniel
That's why is good to have hammer around just in case

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Model Identifier:          MacPro3,1
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PCIe comes up but link width is reduced

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