PXI_CLK10

I just added a PXI-6653 to my PXI-1011 chassis, in slot 2, and am trying to replace the native 10 MHz backplane PXI_CLK10 with the high precision OCXO one in the '6653. The objective is to provide a divided (by factors of 2) reference clock, that has the precision of the OCXO. I am running this in LV 7.1, NI-MAX 4.5 etc.
The vi attached first connects OCXO to PXI_CLK10_IN, thus replacing the native clock with this precision one. That part came from "NI-SYNC Route Clock.vi"
Then, from "NI-SYNC Generate DDS Signal, Divide and Route.vi" the DDS takes the precise PXI_CLK10 from the backplane, and brings it to CLKOUT at full frequency, as well as a lower frequency that is divided by factors of two, to the PFI0 prt.
The problem is that when I measuring the full frequency clock at CLKOUT, it has the (lack of precise) frequency of the native backplane clock, or about +/-4 to 5 ppm. I actually calibrated my fequency counter by porting the OCXO out CLKOUT with the first vi, and it is calibrated to +/- 0.5 ppm now.
Could my problem be compatibility issues with the PXI-1011 chassis? I read in another thread about someone with a PXI-1033, that had to set switch S1. I can't find any S1 or other config switches on this chassis.
Anyone had similar experiences with the PXI-6653 and older chassis?
Thanks in advance for your comments,
Kurt
Solved!
Go to Solution.
Attachments:
My-SYNC Route OCXO To PXI_CLK1 To Control DDS, Divide and Route Rev2.vi ‏82 KB

Dr. K,
I would recommend trying to route the PXI_CLK10 directly to CLK_OUT. Using this route alone should get you the original PXI clock. If you also route the OCXO to PXI_CLK10_IN, you should now be able to verify the more accurate clock. This is eliminating the DDS from the picture. Do you see the increase in accuracy? If not, the clocs are not routing as they should and it may be a chassis problem. If you do see an increase in the clock accuracy, then the routing is working as it should and we can further esplore the DDS side of things.
Let me know what happens.
Regards,
Peter Flores
Applications Engineer

Similar Messages

How do I use the PXI_clk10 backplane clock? It's not there!

Hi, folks!
This might seem a trivial question, but I'm completely at a loss here. I have made an RT-project in LV8 which (among other things) samples data continuously from two cards located in a PXI-system. All 32 (16+16) differential channels are used and one task for each card is configured in MAX. Since signal phase is an issue, I need to synchronize both tasks accurately. The lv8 code examples have a couple of VIs that should have been directly applicable to my situation, and I have studied them (and lots of others) in detail.
I have attached one example below that seemed to be spot on, and it makes use of the external PXI_Clk10 clock located in the pxi backplane. Here the confusion starts. When you attach a constant to the "source" input of the "sample clock" VI you get a drop-down list of possible sources. In the example code, PXI_Clk10 is chosen in this list, but when I try to do the same I discover that this option is simply not present. Only internal timing sources (located on the cards) can be chosen. If I configure the timing of the tasks directly in MAX, the PXI_Clk10 is an available option, but this leads to a vague error message when I start the tasks saying roughly that "it might be that you did not specify a name for the external sample clock...".
I have tried everything. My PXI-settings in MAX, routing signals via PFI-pins (didn't work at all), etc etc.
What is going on? Also: when routing a signal through a pfi-port, does this necessitate connecting the pfi-connectors physically or is the signal routed internally through the backplane? It doesn't help that I use BNC-2110 connector blocks. How can I be sure that the connectors on these blocks actually correspond to the terminals on the cards? I can't find a wiring diagram anywhere on the web.
Some facts: PXI-1031 chassis with PXI-8184 controller (dual boot) and two cards PXI-6229 / PXI-6259. These cards are located in slot 3-4.
Regards, Einar
Attachments:
Multi-Device Synch-Analog Input-Cont Acquisition.vi ‏77 KB

All PXI chassis produce PXI_CLK10 on the backplane (from an on-board 10 MHz oscillator), and most of them can also receive a 10 MHz clock from Slot 2 and broadcast that on the backplane. Some models can receive 10 MHz from a BNC connector on the back. Similarly, both 10 MHz and 100 MHz clocks are always available on PXI Express chassis.
Unfortunately, the 6143 and 6133 have no provision to connect to PXI_CLK10. This is likely because the master clock on those boards is 20 MHz, and there may not have been board space or room in the cost budget for a PLL to lock it to 10 MHz. Many other PXI products can use PXI_CLK10, such as the 6120. There is a list of products which use CLK10 and other PXI features here:
http://digital.ni.com/public.nsf/allkb/F4AD3B87DC8CD62E862571E3007042E5
I suspect this list is a little outdated; perhaps someone reading this knows where a more updated version is.
Hope this helps,
Ed

How to make PXI-6733 use PXI_Clk10 as the Reference Clock?

I'm using PXI-6733 and it is put in the PXIe-1065 Chassis. As you know, the PXIe-1065 has a clock PXI_Clk10 and distributes it to all its slots. Now I want to use the PXI_Clk10 as the reference clock for PXI-6733, meaning I want to lock the PXI-6733 onboard clock to the Chassis clock PXI_Clk10.
The question is that I can't select the PXI_Clk10 as a Ref.Clock. It is not in the list.And I have filter the channel names. Have you ever encounter this problem? Can PXI-6733 use PXI_Clk10?

10MHz is routed via RTSI line. Unfortunately, 6733 doesn't have one.

Pxi_clk10 missing?

Hi,
I'd like to use the PXI_Clk10 signal to synchronize dsa tasks, as per the shipping example Multi-Device-Sync-AI and AO-Shared Timebase & Trig-DSA.vi
The problem is, PXI_Clk10 isn't an available choice from the drop down list of terminals, although I can see it when I create a task in MAX. Where is it? How do I get it? I'm using PXI-4461/4462 devices in a PXI-8196 controller.
Thanks for any help!

Just a guess, but you can right click the name constant and select "I/O Name Filtering" to see other channels. Maybe it is available in the Advanced Terminals.
Hope this helps,
Jon

PXI_Clk10 synchronization

Hello,
I need to synchronize all DAQ cards within my PXI chassis with the same timebase. I managed to do it by routing 20Mhz timebase of a E-series DAQ board through the PXI_Trig7 line of the PXI bus.
It works great, but now my problem is to do the same in the case of multi-chassis configurations. I would need to connect this clock from one DAQ board of the first chassis to the second one, but this would need specific cabling and I think this way is not the most convenient.
I tried to initially synchronize all the cards on my single PXI chassis system on the 10MHz chassis clock, also known as PXI_Clk10, but I discovered this signal was not available for E-series DAQ boards : I tried to route /6040E_1/PXI_Clk10 and it produces an error.
I only saw this signal was available for M-series board or the (very expensive) PXI 6653 boards.
I do not really understand why this signal is not usable with this generation of DAQ boards, as PXI_Clk10 seems to be part of the PXI standard and multi-chassis synchronization is naturally available through BNC chain connection.
As an alternative, I perform routing of PXI_Clk10 from a M-series board in each chassis to the PXI_Trig7 to be used as timebase reference. It works well but my problem is that some of our systems do not have M-series board available...
Is there a simple way to use PXI_Clk10 for any DAQ board installed in a PXI chassis ?
Message Edité par Inpriser le 08-17-2006 04:17 AM

Thanks to all for the responses. I did figure out the problem, and some limitations with the board. After reconfiguring my VI, I found out from NI that the board cannot simultaneously have synchronized output of a digital line with the trigger based upon the analog input and unlimited, continuous acquisition at the same time. I was able to get an output pulse on PFI 1 synchronized with the trigger created by the digitized input, but only for a finite number of requested acquisitions. This still works because the requested number may be very large, and at my acquisition rate of 2000 per second, I can set it to run for several hours before the acquisition total number is reached.
Thanks again,
Mike Hinckley

Can we lock 80 MHz timebase to PXI_CLK10 on PXI-6220 M Series DAQ?

I am using PXI-6220 to measure Frequency/Period of 32768 Hz clock signal, accuracy is very important. I have provided signal to measure on Gate input of Ctr 0 (PFI 9). I am using 80 Mhz Timebase. I want to Lock PLL to PXI back plane 10 MHz reference (PXI_CLK10) which in turn is locked onto the 10 MHz reference via PXI-5600 on Slot 2 (External 10 Mhz standard is connected). so far I don't see a way to lock PLL to PXI_CLK10. Is that possible at all? see the image attached to this message.
Attachments:
M Series DAQ Question.png ‏62 KB

Hello Abhatti,
Based on the diagram that you have attached, the M-Series card can PLL to a higher accuracy clock such as the PXI Clock_10. The way to configure this change using the DAQmx driver is route the signals using the DAQmx Timing RefClk.Src Timing property node. Once you place down this property node, and specify the RefClk.Src attribute, you select the PXI-Clk10 as your reference clock source. This will discipline the 80 MHz Timebase of the DAQ card to the 10 MHz reference clock of the PXI chassis. Which chassis are you using? Also, how have you PLL'ed the 10 MHz backplane clock to the PXI-5600 Downconverter?
Michael L.
Applications Engineer
National Instruments

Using an external reference clock for counter measurements

Hi all,
I have several PXI chassis
configured for testing, each of which uses an NI-DAQ-6221 for
conducting period and frequency measurements among other things.
However each of my setups give me a slightly different reading when conducting identical measurements due to
the tolerance of the DAQ on board reference
clocks.
The chassis' have a 10MHz GPS calibrated reference fed into them via the reference input and this is connected to the backplane. I have tried and failed to try to route and use this as my reference
base for my counter measurements so that each of my cards will give me
the same reading every time. I have tried the routing method using the
DAQ connect terminals vi but could not get this to work. I have looked through the labview examples and cant find anything thta shows me what i need to do to take frequency and period measurments using my external reference as my base clock. There are some examples showing the use of the DAQmx timing vi set to sample clock mode which allows a clock source to be selected. However these examples are only for counting digital events and when i apply the same vi to a frequency or period measurement an error is thrown saying 'invalid timing type for this channel', 'you can select: implicit, on demand'.
I do not
understand the working of the DAQ hardware very well so was hoping
someone could help explain to me how to do this if it is even possible
or give me any guidance as to how else to overcome my problem. Any vis
showing how to use my external 10MHz reference
as the base clock for these kind of measurements would be greatly appreciated.
Regards,
Dan

Hi Dan,
Thanks for the reply. When trying to use the connect terminals i just tried connecting the PXI10 to the onboard clock in the hope that this would configure it to use the PXI10 signal to synchronise the onboard clocks via the PLL. Doing this didn't throw any errors as i recall, it just gave me a reading of infinity as it couldn't measure the signal.
I have actually just managed to successfully do what i wanted thanks to help from Rob at NI tech support UK. There is a DAQmx timing property node which allows you to choose a reference clock source. By using the PXI_Clk10 signal this makes the DAQ synchronise its reference clocks to this signal. I have included an image of the code i used to achieve this to take period measurements.
Here is a very useful link which Rob sent me which may be of help to anyone else with similar problems
http://zone.ni.com/devzone/cda/tut/p/id/3615
Best regards,
Dan.
Attachments:
ExtRef Source Image.jpg ‏105 KB

Timebase synchronization issue with PXI 6713

As indicated in another post, I need to use a common timebase to all cards within my PXI chassis to synchronize my acquisition/generation DAQmx tasks.
I performed that successfully by setting timebases of all boards from the 20MHz timebase of a E-series DAQ board.
I have another system setup where I do not have E-series DAQ boards but only M-series. In this case, I tried to synchronize all the cards with the 10MhzRefClock of a PXI 6254 board. It seemed to work correctly, until I looked at the analog output signal of one PXI 6713 board.
This device has 8 analog outputs, I performed as for DAQ boards : I set its timebase to a 10Mhz clock. When I have at least two outputs with hardware timing I observe on scope really weird signal : nothing is visible when all outputs are left to zero volt, but when another voltage is set, the output toggles at very high frequency between 0V and the setting voltage. When two outputs are set to values different from zero, the output also toggles but between these two settings...
I thought it was a board failure, but I checked with another PXI 6713 and the behavior is the same.
When synchronizing with a 20MHz timebase, everything is fine, but 10MHz clearly shows this issue. I checked the 6713 documentation, and it seems possible to use a timebase different than 20MHz.
I attached a VI that illustrates the problem : I create a DAQmx task containing 2 AOs, where 10MHz timebase is taken from a M-series DAQ board. A hardware timed single point timing is configured and outputs are updated in a while loop. If you connect a scope to the first analog output, you will see the phenomenon.
Everyting is fine when you select a 20MHz clock as a timebase. 10MHz leads to this issue. I also tried to synchronize through PXI backplane clock (i.e. /6259_1/PXI_Clk10) but it leads to the same problem.
Please note that using the same 10MHz synchronization on DAQ cards (PXI 6040E, 6071E, 6254, 6259...) for AO works perfectly. I only encountered this problem with PXI 6713 board.
Message Edité par Inpriser le 08-18-2006 02:54 AM
Attachments:
Synchro 10 MHz PXI AO.vi ‏34 KB

Inpriser,
You wanted to use the PXI 10MHz clock to synchronize to 6713s using the PXI capabilities. I’m afraid that since the AO series doesn't have a PLL, you won't be able to use the PXI 10 clock.
I made a few search and found this:
“Neither the 6713 nor any of the AO series support PLL synchronization. However, the M-Series does, though in that case you are limited to a smaller number of analog outputs. Regardless, the best option is using an Arb or other card that can use the Star Trigger, or an m-series device with PLL synchronization capabilities.”
For more info’s about how to deal with PXI and PLL, please check this forum:
http://forums.ni.com/ni/board/message?board.id=170&message.id=11986&requireLogin=False
I’m sorry to disappoint you, hoping you’ll manage to deal with that,
Regards,
BRAUD Jean-Philippe
Field Sales Engineer - Nord et Centre France
LabVIEW Certified Developper

PXI-5402 to PXI-4498 Synchronizing

I have a PXI-1033 Chassis with a PXI-5402 function generator in slot 2 and a PXI-4498 16 channel simultaneous DAQ in slot 3. I'm controlling in with Labview 2011 64bit though a ExpressCard-8360. I'd like to synchronize it so that DAQ starts collecting data an even number of cycles after my function generator starts.
Ideally it would work like this:
1. Start Function Generator
2. Wait a specified amount of time for the mechanical system to settle
3. Wait until the next cycle of the output from the function generator starts.
4. Gather the required data from the DAQ.
I'd like steps 3 and 4 above to happen with as little delay as possible. Currently I'm doing it like this:
1. Init Function Generator
2. Configure reference clock to PXI_Clock, this is the chassis internal 10Mhz clock
3. Route the front panel Sync_Out to PXI_Trigger Line 0
4. Init the DAQ and create the AI virtual channel
5. Configure the reference clock to PXI_Clk10, this is the chassis internal 10Mhz clock.
I believe that I now have the all the 10Mhz clocks PLL together. Am I correct?
6. Set to True the DAQmx Channel Property AI.RemoveFilterDelay
7. Start the function generator
8. Wait the specified amount of time
9. Setup the sample clock on the DAQ
10. Set the DAQ to trigger on the rising edge of PXI_Trigger Line 0
11. Use DAQmx Control Task to commit these settings
12. Start the Task
13. Read the samples with DAQmx Read
This seems to work well except that I can tell from my data that it takes several 'tick' of the sample clock from the time the trigger fires until the first sample is actually read. Is there a way to reduce or compensate for this time?
Thinga that don't seem possible due to the limitations of the hardware:
Using Sync Triggers are not possible because they are not available on the function generator.
Using the Tclk function since it can't be used with DAQmx
Using the the Start Trigger and setting the AI Delay Time (or whatever it's called) to delay the start of data acquisition since it has the same problems with trigger delay as the sync out
Setting the DAQ to slave because you cannot set the Function generator to Master.
So, finally, is there a better way to do this synchronization that will more closely tie the receipt of the trigger and the beginning of data acquisition?
I've also thought I could use a reference trigger and acquire the necessary number of pretrigger samples but I don't know if it's possible to get the trigger delay time through one of the property nodes. Is there a property node for trigger delay?

Hi Ben Manthey,
By using the dummy read before your actual read gives you the option of how many samples you throw out. The AI.RemoveFilterDelay property node only gets rid of a constant number and you are unable to change that. It seemed like the first couple samples you got were after the zero line and with the dummy read you can control how many are erased and have your first sample right at zero line. In the following link the article discusses more about using the dummy read and its use: http://digital.ni.com/public.nsf/allkb/F989B25FF6CA55C386256CD20056E27D?OpenDocument. Also if you use the analog triggering, you do not have to worry about the extra samples and the following KnowledgeBase article discusses this: http://digital.ni.com/public.nsf/websearch/EA42429C0BF5510C86256DA9007876E3. I have also included the NI Dynamic Signal Acquisition User Manual to provide more information about the triggering of DSA devices: http://digital.ni.com/manuals.nsf/websearch/C7F1AE47873FDE428625773700589591.
Regards,
Tommy G.
Applications Engineer
National Instruments

How To output the PXI-6608 OCXO to PXI_CLK10_IN

Hi!
I am trying to make high accuracy measurements with the PXI-6608.
I am using a 3rd party PXI backplane which has no StarTrigger slot that would override the PXI_CLK10 automatically with the PXI-6608 OCXO output PXI_CLK10_IN.
It appears that the PXI-6608's OCXO has no direct link to the time source of the counters but that instead the time source can "only" be PLL-synced to PXI_CLK10 signal of the backplane. Is this correct?
I tried to measure the high accuracy OCXO output on PXI_CLK10_IN but got nothing. What needs to have the PXI-6608 output its OCXO clock to PXI_CLK10_IN?
ThanXs for your help, Hezapeter

By connecting the OCXO to the PXI_CLK10_IN, you are overriding the PXI clock to make a more accurate reference clock. So anything that is using the PXI clock at a reference will become more accurate. I believe you have to set the source reference clock for the DAQmx tasks to the PXI clock in order to get this benefit.
But here's how you connect the OCXO to the PXI clock.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Attachments:
Connect Clock.png ‏9 KB

Can´t export the SampleClockTimebase signal

Hi fellows, I have the following configuration:
PXI 8105 controller
PXI 1031 Chassis
PXI 4461 DSA in slot 2 (master device)
PXI 4472b in slot 3 (slave device 1)
SW:
LabVIEW 8.2.1
DAQmx 8.5.0f5
I am trying to synchronize both devices by exporting the "SampleClockTimebase" and "SyncPulse" signals from the master (4461) device to the slave (4472b) device. As you can see in the figure 1 attached, I am doing this by letting DAQmx choose the proper lines.
When I run the vi, I have an error code -89120 which says that the line for the "SampleClockTimebase" cannot be found for the device from the Slot2 (i.e. the master device). So I went to see the connections diagram of the 4461 in MAX. As you can see in the figure 2, this diagram show that there is no chance to export the "SampleClockTimebase" signal. In the diagram, I don´t see any PXI_Star lines. I assume that something must be wrong, but I don´t know what can it be.
I have identified the controller and also the chassis in MAX.
Any ideas?
Attachments:
Figure1.jpg ‏78 KB
Figure2.jpg ‏149 KB

Hi again,
in the last link that I gave (http://digital.ni.com/public.nsf/allkb/370156F34082C8AA862571D300671367), from the second paragraph of the Solution section, it is clear that the PXI Star connectivity is not present for hybrid slot compatible 446x devices. However, it is not clear if the Clk10 connectivity is also present or not. It only says (in the third paragraph) that the 447x devices doesn´t support this connectivity and thus, the synchronization between 446x hybrid slot compatible and 447x devices is not possible.
What if I want to synchronize a 446x hybrid-slot compatible device with an M-Series devices who DOES support the PXI_Clk10 connectivity? In the Figure 4 attached bellow, which is the continuation of Figure 1, you can see that the PXI_Clk10 connection is also not available for the 4461 hybrid-slot compatible device.
So, there is no possibility at all for synchronization with standard devices?
thanking in advance,
CJMV
Attachments:
Figure4.jpg ‏144 KB

Synchronizing AI and Counter Tasks in DSA and M Series devices

Hello DAQ fellows, I am new in the Counter field, so it would be really helpful to have your comments and advices about my application.
I need to acquire simultaneouslythe following signals:
- AI Voltage signal with a DSA device (PXI 4461).
- AI voltage signal with a M Series device (PXI 6250).
- Periods between TTL pulses signal with one counter of the same M Series device. I want to use the counter as it is shown in the figure 7-8 attached below.
You can see my approach in the vi attached below (4461-6250ai-6250Ctr.vi). The 4461 is the master device.
For the synchronization between both AI tasks I am using the "SampleClockTimebase" of the master device as a source for the 6250. I am also using the "StartTrigger" signal from the master device to trigger the start of the AI acquisition in the 6250. As I understand, this configuration is OK.
Now come the second stage, which is to include the Ctr task to the acquisition process. I am creating the 3 tasks previously with another vi, the vi which creates the counter task (CreateTask6250Ctr.vi) is also attached. Now in the measurement vi (4461-6250ai-6250Ctr.vi), I use the "SampleClock" of the 6250-AI task in order to synchronize the AI with the Ctr task (I am not sure that this is the proper way to do this). Then I ask the "CounterTimebase.Source" in order to know which one is been used as SOURCE signal for the tick counting between the TTL pulses. Finally, I use the same "StartTrigger" signal from the master device to trigger the start of the Ctr task. In this way, when the AI task from the 4461 is started, it give the "StartTrigger" signal to the AI and Ctr tasks from the 6250 and the 3 start at the same time.
What do you think. am I right with my approach?
Is the Ctr task properly created to use the counter as in figure 7-8?
Are the three tasks properly synchronized?
Which other options do I have in order to synchronize the Ctr task with the other 2?
Thanking in advance,
Cristián
Attachments:
4461-6250ai-6250Ctr.vi ‏1561 KB
Fig 7-8 from M SeriesUserManual.jpg ‏16 KB
CreateTask6250Ctr.vi ‏35 KB

Could I also use the PXI_Clk10 as a "ReferenceClock.Source" for the three tasks in order to synchronize them? I mean, instead of using the "SampleClock" of the AI task of the 6250 and the Ctr tasks of the same device. See the attachment to see what I mean.
Greetings,
Cristián
Attachments:
4461-6250ai-6250Ctr - PXI_Clk10.vi ‏1558 KB

Synchronizing a 6289 with a 4461

I'm trying to output synchronized signals on a 6289 (analog and digital outputs) and a 4461 (only analog outputs) on a PXI chassis (a PXI-1031), but I've been having quite a bit of trouble getting the two devices to synchronize. The 4461 documentation indicates that this device can synchronize to a 10 MHz reference clock:
NI PXI-446X devices employ onboard PLL circuitry. The PLL circuitry locks the onboard 100 MHz voltage-controlled crystal oscillator (VCXO) to the PXI 10 MHz reference clock signal, PXI_CLK10. The VCXO output provides the source for the DDS chip, which generates the sample clock timebase. In this way the NI PXI-446X devices lock the sample clock timebase to PXI_CLK10.
However, I've been unable to access this reference clock directly; I can neither read from it nor write to it. Does this phase-locking occur automatically? If I route PXI_CLK10 to the reference clock input of the 6289, will the two cards be synchronized?
Since I haven't been able to assess whether using the PXI backplane's 10 MHz clock as the 6289's reference clock will synchronize the two cards, I've tried a number of other techniques without much success. The 6289 has an accessible sample clock timebase of 20MHz, while the 4461 has a sample clock timebase of 26.2144 MHz, so these seem to be imcompatible, even if a divisor is used. Additionally, the 6289 does not seem to accept Synchronization Pulses, so even if I could share the timebase (as one would do to synchronize multiple 4472s), the sample clocks on the two cards would be out of phase. If I try to share the Sample Clock directly, I find that the 4461 can only use its onboard clock for the Sample Clock, although I can export the 4461's sample clock to the 6289.
Is there any better way to synchronize these two cards? Thanks.
Jason Rolfe
Jason Rolfe

Rolfe,
The 6289 doesn't have any filters on the Analog Output, so the only filter delays you will have to worry about are on the 4461.
To synchronize the two devices, you have several options. I'll ignore the filter delay on the 4461 for now and come back to it later. First, yes you can use CLK 10 to synchronize both devices. To do this, set the reference clock source to CLK 10 on each device by using the timing property node. For this to work, you will have to have NI-DAQ 7.4 installed since CLK 10 synchronization support for the 4461 was added in this version of the driver. In addition to locking to CLK 10, you will also have to share a start trigger between the two devices. Since there is no trigger support for digital output on the 6289, you will have to use the 6289's ao/sampleClock as the do/sampleClock and start the digital task before the AO task. This solution is nice in that you can output at different rates on the two devices and still maintain phase relationship throughout time.
A second option to CLK 10, is to use the sample clock from the 4461 as the sample clock for the 6289. When using this scheme, you will need to start the digital output and AO task on the 6289 before starting the task on the 4461. This approach is a little more straight forward, but has the disadvantage that it forces all tasks to run at the same sample rate.
Now, we need to address the filter delay on the 4461. So far, the synchronization described above ensures the clocks are synchronized, but it doesn't account for the digital filter delay of the 4461. Depending on the sample rate of the 4461, this filter delay can be 36.6, 36.8, 37.4, 38.5, 40.8, 43.2, 48.0, or 32.0 samples (see the NI Dynamic Signal Acquisition Help for more detailed information). If you are running at a sample rate that doesn't have a fractional sample delay (or you don't care about the fractional delay if it's close enough for you), you have a couple of options. First, you can account for the delay in software by generating waveforms in the software buffers that are already offset by the appropriate sample delay. If you want a hardware driven solution, you can use a start trigger for the AO task on the 6289 and specify a delay from the start trigger of the appropriate number of samples. This can be done through properties under the trigger property node. Using the ao/sampleClock on the 6289 as the sample clock for the digital task will then delay the digital task as well.
If you want to get rid of the fractional delay, you'll have to use the CLK 10 synchronization approach as well as a counter to offset the start of the generations on the 6289 by the appropriate amount. To do this, you'll have to create a counter pulse train task that uses a start trigger. The frequency of the pulse train should match the frequency of the AO sample clock on the 4461. To correct for the filter delay of the 4461, you'll have to calculate the length of time of the filter delay and specify this value as the initial delay for the counter pulse train. The output of the counter is then used to clock both AO and digital tasks on the 6289. The start trigger for the counter task will come from the 4461. So the sequence of events is as follows: 1.) Start the counter, digital, and AO tasks on the 6289, 2.) Start the AO task on the 4461, 3.) The start trigger from the 4461 gets routed to the counter on the 6289, 4.) The counter waits for the initial delay to pass before outputting the pulse train, 5.) The counter starts outputting a pulse train of the same frequency as the sample clock on the 4461 for use by the AO and digital tasks, 6.) The signals on the I/O connector from all three tasks are now synchronized.
Let me know which approach you're leaning towards and I can futher clarify some things if you still have questions. By the way, what sort of application are you developing? I don't typically see this mixture of devices and I/O types.

PXI-6653 DDS ClkIn reference

When I use the example with NI-SYNC called Generate DDS Clock and Route.vi and select DDS Clock Source Terminal: ClkIn, and Destination Terminal: ClkOut, the card does not generate an output clock. If I then click stop, I'm given the error message:
Error -1074118606 occured at niSync Connect Clock Terminals.vi
Driver Status: (Hex 0xBFFA4032) The specified source terminal is invalid for this operation.
If I change the DDS Clock Source Terminal to one of the other sources, I get a signal on ClkOut, but it is not phase locked to my external 10MHz reference oscillator.
How do I generate a DDS clock signal which is phase locked to an external 10MHz reference oscillator connected to ClkIn?
Thanks,
John Bosshard
Solved!
Go to Solution.

Hi John,
You need to use two LabVIEW examples for this task. Run the Check Clk10 & Route Clock.vi first to route ClkIn to the backplane PXI_Clk10. Then run the Generate DDS Clock and Route.vi to route the PXI_Clk10 to ClkOut. This will work as long as your signal meets the backplane 10MHz clock specifications.
Thank you,
Simran K
National Instruments
Applications Engineer

NI 4461 frequency timebase stability

According to “NI Dynamic Signal Acquisition User Manual” NI 4461 card has high-accuracy oscillator. “The oscillator feeds a DDS chip, which is used to generate the other on-board timing signals”. This signal is called the frequency timebase. My question is: Is it possible to replace this signal into another of greater stability and accuracy for example generated on NI 6653?
The second question is: How the stability and accuracy of 10 MHz signal distributed through the PXI bus influences on the stability and accuracy of the frequency timebase and the sample clock timebase generated on NI 4461 card? In my case, NI 4461 operates without synchronization to other devices.

>>Is it possible to replace this signal into another of greater stability and accuracy for example generated on NI 6653?
Yes. You can find an example on page: http://zone.ni.com/devzone/cda/epd/p/id/5059%20he%20will%20install%20NI-SYNC
>> How the stability and accuracy of 10 MHz signal distributed through the PXI bus influences on the stability and accuracy of the frequency timebase and the sample clock timebase generated on NI 4461 card?
If You are not using 10 MHz signal distributed through the PXI bus for NI 4461, it has no influense - card uses it's own clock. You can always override signal on backplane with another one - more accure (for exampel from 6653) and then use it as a reference clock for 4461.
"An NI PXI-6653 or NI PXI-6652 module in Slot 2 of a PXI chassis can
replace the native PXI 10 MHz backplane frequency reference clock
(PXI_CLK10) with the more stable and accurate output of the OCXO or
TCXO. All other PXI modules in the chassis that reference the 10 MHz
backplane clock benefit from this more accurate frequency reference.
Furthermore, the DDS chip on the NI PXI-6653 or NI PXI-6652 references
its output to the backplane clock and also takes advantage of the superior
OCXO or TCXO accuracy. The OCXO or TCXO does not automatically
replace the native 10 MHz clock; this feature must be explicitly enabled in
software. The OCXO or TCXO output also can be routed out to the
CLKOUT connector"
Hope it will help
Best regards
Barbara

PXI_CLK10

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