Referencing bits within a register, using another register

Question

I'm getting an odd error that I don't know how to handle.  I've extracted the relevant code below:
parameter NUM_REG = 9
input [7:0] spi_in,
output reg spi_in_ready, //this module is ready to receive data
output reg [7:0] spi_out,
output reg [(NUM_REG) * 8 - 1:0] register
spi_out <= register[spi_in*8 + 7: spi_in*8];
//error generated: "spi_in is not a constant"
I thought this was allowed... what am I missing? Is there a better means of doing this? The only alternative I see is a large case statement. Functional, but far from elegant!

Answer 1

nleahcim wrote:
As an update, I ran across this thread: http://www.edaboard.com/thread176046.html which suggests that, while you can use a register to specify the index of a single bit, you cannot use a register to specify a range of bits. This seems like an odd limitation to me.
That's not correct, at least not for Verilog 2001.  The problem with Verilog is that you can't use a variable for both ends of a range, i.e. on both sides of the colon in your code.
You have essentially:
  [variable + constant : variable]
and this is not allowed since "variable" appears on both sides of the colon.
You can do the equivalent however using the Verilog 2001 range syntax:
  [variable +: constant]
Where in this case the value of "variable" selects the least significant (rightmost) bit of the part select, and "constant" selects the width of the part select.
Another way is:
  [variable -: constant]
Where in this case the value of "variable" selects the most significant (leftmost) bit of the part select, and "constant" selects the width of the part select.
Note that since "constant is the width in bits, you don't want to subtract one like you would if you were calculating the two ends of the range.  i.e.
  [variable +: 8]
is equivalent to:
 [variable + 7 : variable]
and
  [variable -: 8]
is equivalent to:
  [variable : variable - 7]