Running data at different rates within a SCTL for resource sharing

Question

I have a design that contains several single cycle timed loops (SCTL):
(40MHz SCTL) -> (20MHz SCTL) -> (40MHz SCTL) -> (10MHz SCTL)
The first 2 SCTLs are decimation filters so that the data coming out of the 20MHz SCTL is
at a 10MHz sampling rate.  The 2ns 40MHz SCTL is filter that is 4X resource
shared so that I can use the available dsp48E slices.  I'm using target-scoped FIFOs to
pass the data between the loops.  In simulation, I have the timeout set to -1 so that it reads
from the FIFO whenever there is data available.
When I run the simulation, I expect/want to see my control counter running 4 times faster
than my incoming data.  I thought that since the data was written into the target-scoped
FIFO at a 10MHz rate and the control counter is in the 40MHz SCTL, I would see the
behavior I wanted:
    X     a     X     b      X      c     X     d     X  <- data from FIFO
    X0X1X2X3X0X1X2X3X0X1X2X3X0X1X2X3X  <- modulo-3 counter
Instead I see the data and counter essentially running at the same rate:
    X1X2X3X4X5X6X7X8X9XaXbXcXdXeXf X0X    <-data from FIFO
    X0X1X2X3X0X1X2X3X0X1X2X3X0X1X2X3X    <-modulo-3 counter
Also the iteration counter for the SCTL runs at the same rate which seems to indicate that the
loop only executes when data is pulled from the FIFO.   I was expecting the iteration counter
to be at 3 before the second sample was read from the FIFO and at 7 before the third sample
was read from the FIFO. I'm guessing that the simulator is event driven.
I have a couple of questions:
1. How can I  get the behavior I'm looking for?
2. If not, can I expect the behavior I want if I run this on the hardware?

Answer 1

update:
NI support suggested using the FIFO timeout signal to determine when the data is valid
coming out of the FIFO.  I was using a -1 on the FIFO read to read only when a sample
was available.  NI support said to use a 0 and then gate the data based on the timeout
signal.  The behavior of the design changed, but still did not give me the timing I was
expecting.  Instead of seeing my counter update on every new sample, I see the SCTL
"free running"  It's difficult to determine if the counter is behaving properly, but I do see it
running faster.  The problem is that the SCTL seems to be running much faster was well.
Using the -1 on the FIFO read I would see > 262K samples written out for every 1000 in.
Using the 0 on the FIFO read and gating the data based on the timeout signal, I see
>60K samples for every 1000 read in. I'm expecting 250 samples out for every 1000 in.
Can someone tell me what controls the behavior (in terms of execution0 of the SCTL?  It
seems like it is event driven, but I need the design to be clock or cycle driven for both
simulation and execution of the hardware.
Regards,